JPS61192311U - - Google Patents
Info
- Publication number
- JPS61192311U JPS61192311U JP7423485U JP7423485U JPS61192311U JP S61192311 U JPS61192311 U JP S61192311U JP 7423485 U JP7423485 U JP 7423485U JP 7423485 U JP7423485 U JP 7423485U JP S61192311 U JPS61192311 U JP S61192311U
- Authority
- JP
- Japan
- Prior art keywords
- output
- terminal
- input terminal
- resistor
- series circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000087 stabilizing effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Control Of Electrical Variables (AREA)
Description
第１図は本考案にかかる安定化電源回路の一実
施例を示す回路図、第２図は本考案による各入・
出力の関係を示す特性図、第３図は従来の安定化
電源回路の一例を示す回路図、第４図は他の従来
回路を示す回路図である。
１……入力端子、２……出力電圧端子、３……
リセツト出力端子、３１，３２……トランジスタ
、３３，３５〜３７……抵抗、３４……ツエナダ
イオード。
Figure 1 is a circuit diagram showing an embodiment of the stabilized power supply circuit according to the present invention, and Figure 2 is a circuit diagram showing each input/output circuit according to the present invention.
A characteristic diagram showing the relationship between outputs, FIG. 3 is a circuit diagram showing an example of a conventional stabilized power supply circuit, and FIG. 4 is a circuit diagram showing another conventional circuit. 1...Input terminal, 2...Output voltage terminal, 3...
Reset output terminal, 31, 32...Transistor, 33, 35-37...Resistor, 34...Zena diode.
Claims (1)
第１の出力端子に安定化して出力するとともに、
第２の出力端子にリセツトパルスを出力するよう
にした安定化電源回路で、 上記入力端子に一端が接続され、他端が第１の
出力端子に接続された第１の抵抗と、 第２の抵抗及びツエナダイオードを互いに直列
に接続し、第２の抵抗側を上記入力端子に接続す
るとともにツエナダイオード側を基準電位点に接
続して成る直列回路と、 コレクタ・エミツタ間が上記第１の出力端子と
基準電位点との間に接続され、ベースが上記直列
回路の交点に接続された第１のトランジスタと、 コレクタ・エミツタ間が上記入力端子と第２の
出力端子との間に接続され、ベースが上記直列回
路の交点に接続された第２のトランジスタとを具
備して成る安定化電源回路。[Claims for Utility Model Registration] The voltage from the input terminal to which the rectified output is supplied,
While stabilizing and outputting to the first output terminal,
A stabilized power supply circuit configured to output a reset pulse to a second output terminal, the first resistor having one end connected to the input terminal and the other end connected to the first output terminal; A series circuit in which a resistor and a Zener diode are connected in series, the second resistor side is connected to the input terminal, and the Zener diode side is connected to a reference potential point, and the collector-emitter is connected to the first output. a first transistor connected between the terminal and a reference potential point, the base of which is connected to the intersection of the series circuit; and a collector-emitter connected between the input terminal and a second output terminal; and a second transistor whose base is connected to the intersection of the series circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7423485U JPS61192311U (en) | 1985-05-21 | 1985-05-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7423485U JPS61192311U (en) | 1985-05-21 | 1985-05-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61192311U true JPS61192311U (en) | 1986-11-29 |
Family
ID=30614340
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7423485U Pending JPS61192311U (en) | 1985-05-21 | 1985-05-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61192311U (en) |
-
1985
- 1985-05-21 JP JP7423485U patent/JPS61192311U/ja active Pending
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