JPS61184334U - - Google Patents
Info
- Publication number
- JPS61184334U JPS61184334U JP6860585U JP6860585U JPS61184334U JP S61184334 U JPS61184334 U JP S61184334U JP 6860585 U JP6860585 U JP 6860585U JP 6860585 U JP6860585 U JP 6860585U JP S61184334 U JPS61184334 U JP S61184334U
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- transistor
- resistor connected
- collector
- ground
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 230000007257 malfunction Effects 0.000 claims 1
- 230000002265 prevention Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Description
第１図は本考案の一実施例の回路図である。
１，２……電源供給端子、３……出力端子、Ｒ
１，Ｒ２……抵抗、Ｄ……ツエナーダイオード、
Ｑ……ＰＮＰ型トランジスタ、Ｃ……コンデンサ
。
FIG. 1 is a circuit diagram of an embodiment of the present invention. 1, 2...Power supply terminal, 3...Output terminal, R
1, R2...Resistor, D...Zener diode,
Q...PNP transistor, C...capacitor.
Claims (1)
０”又は“１”にするＰＮＰ型のトランジスタと
、前記エミツタと第１の電源との間に接続してあ
る第１の抵抗と、前記エミツタと前記トランジス
タのコレクタとの間に接続してあるコンデンサと
、前記トランジスタのベースと接地との間に接続
してある第２の抵抗と、前記ベースと第２の電源
との間に接続してあるツエナーダイオードとが備
えてあり、前記コレクタは前記接地に接続してあ
り、前記第１及び第２の電源の電圧が正常である
か異常に低いかを表す論理信号を前記エミツタか
ら出力することを特徴とする誤動作防止回路。 The logic state of the emitter voltage is changed depending on the conduction state.
a PNP type transistor to be set to 0" or "1"; a first resistor connected between the emitter and a first power source; and a first resistor connected between the emitter and the collector of the transistor. a capacitor, a second resistor connected between the base of the transistor and ground, and a Zener diode connected between the base and a second power supply, and the collector is connected to the A malfunction prevention circuit, which is connected to ground and outputs a logic signal from the emitter indicating whether the voltages of the first and second power supplies are normal or abnormally low.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6860585U JPS61184334U (en) | 1985-05-09 | 1985-05-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6860585U JPS61184334U (en) | 1985-05-09 | 1985-05-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61184334U true JPS61184334U (en) | 1986-11-17 |
Family
ID=30603501
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6860585U Pending JPS61184334U (en) | 1985-05-09 | 1985-05-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61184334U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5546654A (en) * | 1978-09-29 | 1980-04-01 | Toshiba Corp | Initialization circuit |
-
1985
- 1985-05-09 JP JP6860585U patent/JPS61184334U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5546654A (en) * | 1978-09-29 | 1980-04-01 | Toshiba Corp | Initialization circuit |
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