JPH0193813U - - Google Patents
Info
- Publication number
- JPH0193813U JPH0193813U JP18875887U JP18875887U JPH0193813U JP H0193813 U JPH0193813 U JP H0193813U JP 18875887 U JP18875887 U JP 18875887U JP 18875887 U JP18875887 U JP 18875887U JP H0193813 U JPH0193813 U JP H0193813U
- Authority
- JP
- Japan
- Prior art keywords
- muting
- resistor
- capacitor
- transistor
- controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Amplifiers (AREA)
Description
第１図は本考案の一実施例を示す図、第２図は
従来例を示す図である。
１……コントローラ、２６……コンデンサ、２
７……第１抵抗、２８……トランジスタ、２９…
…第２抵抗、３０……第３抵抗、３１……ツエナ
ーダイオード。
FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional example. 1... Controller, 26... Capacitor, 2
7...First resistor, 28...Transistor, 29...
...Second resistor, 30...Third resistor, 31...Zener diode.
Claims (1)
へミユーテイング制御信号を出力するコントロー
ラと、電源供給線路とアース間に直列に接続され
たコンデンサ及び第１抵抗と、同じく電源供給線
路とアース間に直列に接続されたトランジスタと
第２及び第３抵抗と、前記コンデンサ及び第１低
抗の接続中点と前記トランジスタのベースとの間
に配設された定電圧素子とを具備し、前記第２及
び第３抵抗の両端に発生する電圧をミユーテイン
グ制御信号としてミユーテイング回路へ供給する
と共に前記第３抵抗の両端に発生する電圧をイン
ヒビツト信号として前記コントローラへ供給する
ようになしたことを特徴とするミユーテイング回
路。 At least a controller that outputs a muting control signal to the muting circuit when the power is turned on, a capacitor and a first resistor connected in series between the power supply line and the ground, and a transistor also connected in series between the power supply line and the ground. a constant voltage element disposed between a connection midpoint of the capacitor and the first low resistor and a base of the transistor; A muting circuit characterized in that the generated voltage is supplied to the muting circuit as a muting control signal, and the voltage generated across the third resistor is supplied as an inhibit signal to the controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18875887U JPH0193813U (en) | 1987-12-10 | 1987-12-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18875887U JPH0193813U (en) | 1987-12-10 | 1987-12-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0193813U true JPH0193813U (en) | 1989-06-20 |
Family
ID=31479831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18875887U Pending JPH0193813U (en) | 1987-12-10 | 1987-12-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0193813U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS619909B2 (en) * | 1977-08-04 | 1986-03-26 | Daihen Kk |
-
1987
- 1987-12-10 JP JP18875887U patent/JPH0193813U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS619909B2 (en) * | 1977-08-04 | 1986-03-26 | Daihen Kk |