JPS6168517U - - Google Patents
Info
- Publication number
- JPS6168517U JPS6168517U JP15299684U JP15299684U JPS6168517U JP S6168517 U JPS6168517 U JP S6168517U JP 15299684 U JP15299684 U JP 15299684U JP 15299684 U JP15299684 U JP 15299684U JP S6168517 U JPS6168517 U JP S6168517U
- Authority
- JP
- Japan
- Prior art keywords
- parallel
- diodes
- generation circuit
- distortion generation
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Filters And Equalizers (AREA)
- Transmitters (AREA)
Description
第1図は本考案による歪発生回路の実施例を示
す回路図である。
1,2…ダイオード、3〜6…抵抗器、7〜9
…コンデンサ、10,11…チヨークコイル。
FIG. 1 is a circuit diagram showing an embodiment of a distortion generating circuit according to the present invention. 1, 2...Diode, 3~6...Resistor, 7~9
...Capacitor, 10,11...Chiyoke coil.
Claims (1)
る歪発生回路において、2ケのダイオードのそれ
ぞれに抵抗器を並列接続した回路を直流的に直列
接続し、この接続点を信号の入力または出力端と
し、前記並列接続した回路の他端同士を高周波的
に接続して信号の一方の端子とし、前記並列接続
した回路の他端にそれぞれ抵抗器またはチヨーク
コイルを介して直流バイアス電流を印加するよう
に構成したことを特徴とする歪発生回路。 In a distortion generation circuit that uses two diodes in parallel with opposite polarities, a circuit in which a resistor is connected in parallel to each of the two diodes is connected in series with DC, and this connection point is used as a signal input or output. The other ends of the parallel-connected circuits are connected at high frequency to serve as one terminal of the signal, and a DC bias current is applied to the other ends of the parallel-connected circuits through resistors or chiyoke coils, respectively. A distortion generation circuit characterized in that it is configured as follows.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15299684U JPH0230912Y2 (en) | 1984-10-09 | 1984-10-09 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15299684U JPH0230912Y2 (en) | 1984-10-09 | 1984-10-09 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6168517U true JPS6168517U (en) | 1986-05-10 |
JPH0230912Y2 JPH0230912Y2 (en) | 1990-08-21 |
Family
ID=30711033
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15299684U Expired JPH0230912Y2 (en) | 1984-10-09 | 1984-10-09 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0230912Y2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003347942A (en) * | 2002-05-28 | 2003-12-05 | Matsushita Electric Ind Co Ltd | Transmission power control apparatus and transmission power control method |
US7557654B2 (en) | 2004-10-28 | 2009-07-07 | Mitsubishi Electric Corporation | Linearizer |
JP2012015860A (en) * | 2010-07-01 | 2012-01-19 | Univ Of Electro-Communications | Distortion compensation circuit |
-
1984
- 1984-10-09 JP JP15299684U patent/JPH0230912Y2/ja not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003347942A (en) * | 2002-05-28 | 2003-12-05 | Matsushita Electric Ind Co Ltd | Transmission power control apparatus and transmission power control method |
US7557654B2 (en) | 2004-10-28 | 2009-07-07 | Mitsubishi Electric Corporation | Linearizer |
JP2012015860A (en) * | 2010-07-01 | 2012-01-19 | Univ Of Electro-Communications | Distortion compensation circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0230912Y2 (en) | 1990-08-21 |
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