JPS62203523U - - Google Patents
Info
- Publication number
- JPS62203523U JPS62203523U JP1986092775U JP9277586U JPS62203523U JP S62203523 U JPS62203523 U JP S62203523U JP 1986092775 U JP1986092775 U JP 1986092775U JP 9277586 U JP9277586 U JP 9277586U JP S62203523 U JPS62203523 U JP S62203523U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- reset
- pulse
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Pulse Circuits (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
Description
第１図は本考案の原理ブロツク図、第２図は本
考案の一実施例を示す図、第３図は第２図のタイ
ムチヤート、第４図は従来例の図である。
図に於いて、３はカウンター回路、４はデコー
ダー回路、５は双安定回路、３０１〜３０３はフ
リツプフロツプ、４０１はＮＡＮＤゲート、Ｃは
コンデンサー、Ｒは抵抗、１２は単安定マルチバ
イブレータを示す。
FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a time chart of FIG. 2, and FIG. 4 is a diagram of a conventional example. In the figure, 3 is a counter circuit, 4 is a decoder circuit, 5 is a bistable circuit, 301 to 303 are flip-flops, 401 is a NAND gate, C is a capacitor, R is a resistor, and 12 is a monostable multivibrator.
Claims (1)
されるクロツク１によりカウントするカウンター
回路３と、 該カウンター回路３の出力をデコードするデコ
ーダー回路４と、 該入力されるパルス２によりリセツトされ、該
デコーダー回路４のデコード出力によりセツトさ
れ、所定の幅のパルス出力６を発生させる双安定
回路５とから成る信号変換回路。[Claims for Utility Model Registration] A counter circuit 3 which is reset by the input pulse 2 and counts by the input clock 1; a decoder circuit 4 which decodes the output of the counter circuit 3; and the input pulse 2. and a bistable circuit 5 which is reset by the decoding output of the decoder circuit 4 and generates a pulse output 6 having a predetermined width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986092775U JPS62203523U (en) | 1986-06-18 | 1986-06-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986092775U JPS62203523U (en) | 1986-06-18 | 1986-06-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62203523U true JPS62203523U (en) | 1987-12-25 |
Family
ID=30954783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986092775U Pending JPS62203523U (en) | 1986-06-18 | 1986-06-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62203523U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5325346A (en) * | 1976-08-20 | 1978-03-09 | Matsushita Electric Ind Co Ltd | Digital delay circuit |
-
1986
- 1986-06-18 JP JP1986092775U patent/JPS62203523U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5325346A (en) * | 1976-08-20 | 1978-03-09 | Matsushita Electric Ind Co Ltd | Digital delay circuit |
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