JPS61143337U - - Google Patents

Info

Publication number
JPS61143337U
JPS61143337U JP2669885U JP2669885U JPS61143337U JP S61143337 U JPS61143337 U JP S61143337U JP 2669885 U JP2669885 U JP 2669885U JP 2669885 U JP2669885 U JP 2669885U JP S61143337 U JPS61143337 U JP S61143337U
Authority
JP
Japan
Prior art keywords
clock pulses
timer
type
counter
switched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2669885U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2669885U priority Critical patent/JPS61143337U/ja
Publication of JPS61143337U publication Critical patent/JPS61143337U/ja
Pending legal-status Critical Current

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  • Electronic Switches (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本考案の一実施例を示す回路図である。 10,11,12,13はインバータ素子、1
4は2入力OR素子、15は2入力NAND素子
、16はインバータ素子、17,18は抵抗、1
9はコンデンサ、20,21はバイナリーカウン
タ、22,23,24,25は2入力AND素子
、26は4入力OR素子、27はバイナリーカウ
ンタ。
The drawing is a circuit diagram showing an embodiment of the present invention. 10, 11, 12, 13 are inverter elements, 1
4 is a 2-input OR element, 15 is a 2-input NAND element, 16 is an inverter element, 17 and 18 are resistors, 1
9 is a capacitor, 20 and 21 are binary counters, 22, 23, 24 and 25 are two-input AND elements, 26 is a four-input OR element, and 27 is a binary counter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 無安定マルチバイブレータより発生させたクロ
ツクパルスをカウンターにて積算、分周し、タイ
マーとして設定したい周期を持つクロツクパルス
を必要種類に応じて発生せしめ、これをその種類
に等しい極を有するデイツプスイツチを切り換え
ることにより、設定時間をその種類の中で任意に
切り換えられることを特徴とするタイマー。
The clock pulses generated by the astable multivibrator are integrated and frequency-divided by a counter, the clock pulses with the period desired to be set as a timer are generated according to the required type, and this is switched by a deep switch having a pole equal to that type. , a timer characterized in that the set time can be changed arbitrarily among the types.
JP2669885U 1985-02-26 1985-02-26 Pending JPS61143337U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2669885U JPS61143337U (en) 1985-02-26 1985-02-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2669885U JPS61143337U (en) 1985-02-26 1985-02-26

Publications (1)

Publication Number Publication Date
JPS61143337U true JPS61143337U (en) 1986-09-04

Family

ID=30522952

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2669885U Pending JPS61143337U (en) 1985-02-26 1985-02-26

Country Status (1)

Country Link
JP (1) JPS61143337U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62269515A (en) * 1986-05-19 1987-11-24 Omron Tateisi Electronics Co Timer device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5485663A (en) * 1977-12-20 1979-07-07 Matsushita Electric Ind Co Ltd Electronic timer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5485663A (en) * 1977-12-20 1979-07-07 Matsushita Electric Ind Co Ltd Electronic timer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62269515A (en) * 1986-05-19 1987-11-24 Omron Tateisi Electronics Co Timer device

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