JPH0485934U - - Google Patents
Info
- Publication number
- JPH0485934U JPH0485934U JP12876290U JP12876290U JPH0485934U JP H0485934 U JPH0485934 U JP H0485934U JP 12876290 U JP12876290 U JP 12876290U JP 12876290 U JP12876290 U JP 12876290U JP H0485934 U JPH0485934 U JP H0485934U
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuit
- packet data
- pulse
- edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 1
- 230000000630 rising effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Description
第１図は本考案の一実施例の回路図、第２図お
よび第３図はそれぞれ第１図の動作を示すタイミ
ングチヤートである。
１，２，６……フリツプフロツプ、３……ＥＸ
−ＯＲゲート、４……インバータ、５……ＢＣＤ
カウンタ。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIGS. 2 and 3 are timing charts showing the operation of FIG. 1, respectively. 1, 2, 6...flipflop, 3...EX
-OR gate, 4...Inverter, 5...BCD
counter.
Claims (1)
ケツトデータの送信・受信を行う回路において、
パケツトデータ内のデータ波形の立ち上がりもし
くは立ち下がりエツジを検出し各エツジに対応し
た一定のパルスを発生する回路と、前記パルスを
起動信号としパケツトデータ内のデータエツジ間
隔を計測し、あるクロツクビツト時間以上パケツ
トデータ内のデータ波形の極性に変化がないとき
これに対応したパルス信号を発生する回路とを有
することを特徴とする信号検出回路。 In a circuit that transmits and receives packet data of NRZI encoding system having a flag pattern,
A circuit detects the rising or falling edge of a data waveform in packet data and generates a constant pulse corresponding to each edge, and uses the pulse as a starting signal to measure the data edge interval in the packet data, 1. A signal detection circuit comprising: a circuit that generates a pulse signal corresponding to a data waveform when there is no change in polarity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12876290U JPH0485934U (en) | 1990-11-29 | 1990-11-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12876290U JPH0485934U (en) | 1990-11-29 | 1990-11-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0485934U true JPH0485934U (en) | 1992-07-27 |
Family
ID=31876205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12876290U Pending JPH0485934U (en) | 1990-11-29 | 1990-11-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0485934U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60235548A (en) * | 1984-05-08 | 1985-11-22 | Nec Corp | Transmission system of signal frame |
| JPH02241111A (en) * | 1989-03-14 | 1990-09-25 | Fujitsu Ltd | Signal interruption detection circuit |
-
1990
- 1990-11-29 JP JP12876290U patent/JPH0485934U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60235548A (en) * | 1984-05-08 | 1985-11-22 | Nec Corp | Transmission system of signal frame |
| JPH02241111A (en) * | 1989-03-14 | 1990-09-25 | Fujitsu Ltd | Signal interruption detection circuit |
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