JPH0378946U - - Google Patents

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Publication number
JPH0378946U
JPH0378946U JP14036889U JP14036889U JPH0378946U JP H0378946 U JPH0378946 U JP H0378946U JP 14036889 U JP14036889 U JP 14036889U JP 14036889 U JP14036889 U JP 14036889U JP H0378946 U JPH0378946 U JP H0378946U
Authority
JP
Japan
Prior art keywords
data
registers
timing signal
judgment
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14036889U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14036889U priority Critical patent/JPH0378946U/ja
Publication of JPH0378946U publication Critical patent/JPH0378946U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案に係る入力フイルタの一実施
例を示すブロツク構成図、第2図は第1図及び第
3図の動作を説明するための各部における波形の
タイムチヤート、第3図は従来の入力フイルタの
一例を示すブロツク構成図である。 3,4,5,6……レジスタ、7……カウンタ
、8……移動平均回路、10,11,12,13
,14……データ比較器、15……判断回路。
Fig. 1 is a block configuration diagram showing one embodiment of the input filter according to this invention, Fig. 2 is a time chart of waveforms at various parts to explain the operation of Figs. 1 and 3, and Fig. 3 is a conventional filter. FIG. 2 is a block configuration diagram showing an example of an input filter of FIG. 3, 4, 5, 6...Register, 7...Counter, 8...Moving average circuit, 10, 11, 12, 13
, 14...data comparator, 15...judgment circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] タイミング信号に基づいて周期計測を行うカウ
ンタ7と、上記タイミング信号に基づいて順次デ
ータをラツチする複数のレジスタ3,4,5,6
と、これらカウンタおよび複数のレジスタの相互
に隣合うデータを比較するデータ比較器10,1
1,12,13,14と、このデータ比較器から
の比較結果に基づいてデータが増加および減少傾
向にあるかまたは安定状態にあるかを判断する判
断回路15と、この判断回路よりの判断出力に基
づいてフイルタを大きくするかまたは小さくする
移動平均回路8とを備えた入力フイルタ。
A counter 7 that measures the period based on a timing signal, and a plurality of registers 3, 4, 5, 6 that sequentially latches data based on the timing signal.
and data comparators 10 and 1 that compare mutually adjacent data of these counters and a plurality of registers.
1, 12, 13, and 14, a judgment circuit 15 that judges whether the data is increasing or decreasing or in a stable state based on the comparison result from the data comparator, and a judgment output from this judgment circuit. and a moving average circuit 8 that increases or decreases the filter based on the input filter.
JP14036889U 1989-12-04 1989-12-04 Pending JPH0378946U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14036889U JPH0378946U (en) 1989-12-04 1989-12-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14036889U JPH0378946U (en) 1989-12-04 1989-12-04

Publications (1)

Publication Number Publication Date
JPH0378946U true JPH0378946U (en) 1991-08-12

Family

ID=31687348

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14036889U Pending JPH0378946U (en) 1989-12-04 1989-12-04

Country Status (1)

Country Link
JP (1) JPH0378946U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5448166U (en) * 1977-09-08 1979-04-03

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57189071A (en) * 1981-05-18 1982-11-20 Mazda Motor Corp Display driver for digital speedometer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57189071A (en) * 1981-05-18 1982-11-20 Mazda Motor Corp Display driver for digital speedometer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5448166U (en) * 1977-09-08 1979-04-03

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