JPH0398531U - - Google Patents
Info
- Publication number
- JPH0398531U JPH0398531U JP640290U JP640290U JPH0398531U JP H0398531 U JPH0398531 U JP H0398531U JP 640290 U JP640290 U JP 640290U JP 640290 U JP640290 U JP 640290U JP H0398531 U JPH0398531 U JP H0398531U
- Authority
- JP
- Japan
- Prior art keywords
- counter
- clock
- digital comparator
- circuit
- divided
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Manipulation Of Pulses (AREA)
Description
第1図はこの考案の一実施例によるデイジタル
コンパレータ回路を示す回路図、第2図は第1図
の回路各部の信号を示すタイミングチヤート図、
第3図は従来のデイジタルコンパレータ回路を示
す回路図である。
3……カウンタ、4……デイジタルコンパレー
タ、6……出力回路(Dフリツプフロツプ)、9
……1/n分周器(1/2分周期)、11……クロ
ツク選択回路(RSフリツプフロツプ)。なお、
図中、同一符号は同一、または相当部分を示す。
FIG. 1 is a circuit diagram showing a digital comparator circuit according to an embodiment of the invention, FIG. 2 is a timing chart showing signals of various parts of the circuit in FIG. 1,
FIG. 3 is a circuit diagram showing a conventional digital comparator circuit. 3...Counter, 4...Digital comparator, 6...Output circuit (D flip-flop), 9
...1/n frequency divider (1/2 period), 11...clock selection circuit (RS flip-flop). In addition,
In the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
カウントするカウンタと、このカウンタのカウン
ト値を設定値と比較するデイジタルコンパレータ
と、このデイジタルコンパレータの出力を上記入
力されるパルスのタイミングで出力する出力回路
とを備えたデイジタルコンパレータ回路において
、上記基準クロツクから1/n分周したクロツク
を生成する1/n分周器と、上記カウンタのカウ
ント値が上記設定値を超えない場合には、上記1
/n分周したクロツクを選択して上記カウンタに
計数させ、一方、上記設定値を超えた場合には、
上記基準クロツクを上記カウンタに計数させ、こ
のカウンタの設定カウント値に達したタイミング
で、上記1/n分周したクロツクのカウントを再
開させるクロツク選択回路とを設けたことを特徴
とするデイジタルコンパレータ回路。 A counter that counts the period of the input pulse using a reference clock, a digital comparator that compares the count value of this counter with a set value, and an output circuit that outputs the output of this digital comparator at the timing of the input pulse. In the digital comparator circuit equipped with a 1/n frequency divider that generates a clock whose frequency is divided by 1/n from the reference clock, and when the count value of the counter does not exceed the set value,
/n divided clock is selected and counted by the above counter, and on the other hand, if the above set value is exceeded,
A digital comparator circuit comprising: a clock selection circuit that causes the counter to count the reference clock, and restarts counting of the 1/n divided clock at the timing when the counter reaches a set count value. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP640290U JPH0398531U (en) | 1990-01-26 | 1990-01-26 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP640290U JPH0398531U (en) | 1990-01-26 | 1990-01-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0398531U true JPH0398531U (en) | 1991-10-14 |
Family
ID=31510078
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP640290U Pending JPH0398531U (en) | 1990-01-26 | 1990-01-26 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0398531U (en) |
-
1990
- 1990-01-26 JP JP640290U patent/JPH0398531U/ja active Pending
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