JPS6170210U - - Google Patents
Info
- Publication number
- JPS6170210U JPS6170210U JP1984154787U JP15478784U JPS6170210U JP S6170210 U JPS6170210 U JP S6170210U JP 1984154787 U JP1984154787 U JP 1984154787U JP 15478784 U JP15478784 U JP 15478784U JP S6170210 U JPS6170210 U JP S6170210U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- count value
- speed control
- control device
- latch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 7
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Control Of Velocity Or Acceleration (AREA)
- Control Of Electric Motors In General (AREA)
Description
第１図は本考案の速度制御装置のブロツク図、
第２図及び第３図はそのタイミングチヤート、第
４図は従来の速度制御装置のブロツク図、第５図
及び第６図はそのタイミングチヤート、第７図は
やはり従来の速度制御装置のブロツク図である。
１…生成回路、２，５…計数回路、３…ラツチ
回路、６…分周回路、７，８…比較回路、９…演
算回路、１２，２０…速度制御装置、２２…回転
数検出回路、３０…最大値検出回路、３１…フリ
ツプフロツプ。
Figure 1 is a block diagram of the speed control device of the present invention.
2 and 3 are timing charts thereof, FIG. 4 is a block diagram of a conventional speed control device, FIGS. 5 and 6 are timing charts thereof, and FIG. 7 is a block diagram of a conventional speed control device. It is. DESCRIPTION OF SYMBOLS 1... Generation circuit, 2, 5... Counting circuit, 3... Latch circuit, 6... Frequency division circuit, 7, 8... Comparison circuit, 9... Arithmetic circuit, 12, 20... Speed control device, 22... Rotation speed detection circuit, 30...Maximum value detection circuit, 31...Flip-flop.
Claims (1)
数回路と、該計数回路の計数値をラツチするラツ
チ回路と、制御されるべき速度に対応した周波数
の信号のエツジ情報より、該計数回路の計数値を
リセツトするリセツト信号と、該ラツチ回路に該
計数回路の計数値をラツチさせるラツチ信号とを
生成する生成回路と、制御されるべき速度の基準
値を設定する設定回路と、該ラツチ回路によりラ
ツチされた値と該設定回路に設定された該基準値
とを比較し、その誤差に対応した信号を出力する
比較回路とを備える速度制御装置において、該計
数回路の計数値が最大計数値に達したとき該ラツ
チ回路に該最大計数値がラツチされるようにする
ことを特徴とする速度制御装置。 (2) 該速度制御装置は該計数回路の計数値が該
最大計数値に達したことを検出する検出回路を有
し、該検出回路は該最大計数値に達したことが検
出されたとき、該ラツチ回路に該計数回路の計数
値をラツチさせるラツチ信号を出力することを特
徴とする実用新案登録請求の範囲第１項記載の速
度制御装置。 (3) 該速度制御装置は該計数回路の計数値が該
最大計数値に達したことを検出する検出回路を有
し、該検出回路は該最大計数値に達したことが検
出されたとき、以後該リセツト信号が入力される
まで該計数回路に該クロツクパルスが入力されな
いようにすることを特徴とする実用新案登録請求
の範囲第１項記載の速度制御装置。 (4) 該検出回路は該計数回路の計数値が該最大
計数値に達したときセツトされ、該リセツト信号
によりリセツトされるフリツプフロツプを有する
ことを特徴とする実用新案登録請求の範囲第２項
又は第３項記載の速度制御装置。 (5) 該計数回路は該最大計数値に達したとき以
後該リセツト信号が入力されるまでその計数値を
変化させないことを特徴とする実用新案登録請求
の範囲第１項記載の速度制御装置。 (6) 該設定回路は該クロツクパルスと位相が同
期したパルスを計数する他の計数回路を含むこと
を特徴とする実用新案登録請求の範囲第１項乃至
第５項のいずれかに記載の速度制御装置。 (7) 該計数回路と該設定回路の他の計数回路と
は該最大計数値が等しいことを特徴とする実用新
案登録請求の範囲第６項記載の速度制御装置。[Claims for Utility Model Registration] (1) A counting circuit that counts clock pulses with a fixed frequency, a latch circuit that latches the counted value of the counting circuit, and edge information of a signal with a frequency corresponding to the speed to be controlled. , a generation circuit that generates a reset signal for resetting the count value of the counting circuit and a latch signal for causing the latch circuit to latch the count value of the counting circuit, and a setting circuit that sets a reference value of the speed to be controlled. and a comparison circuit that compares the value latched by the latch circuit with the reference value set in the setting circuit and outputs a signal corresponding to the error, A speed control device characterized in that when a numerical value reaches a maximum count value, the maximum count value is latched in the latch circuit. (2) The speed control device has a detection circuit that detects that the count value of the counting circuit has reached the maximum count value, and when the detection circuit detects that the count value of the counting circuit has reached the maximum count value, The speed control device according to claim 1, wherein the speed control device outputs a latch signal that causes the latch circuit to latch the count value of the counting circuit. (3) The speed control device has a detection circuit that detects that the count value of the counting circuit has reached the maximum count value, and when the detection circuit detects that the count value of the counting circuit has reached the maximum count value, 2. The speed control device according to claim 1, wherein the clock pulse is not input to the counting circuit until the reset signal is input thereafter. (4) The detection circuit has a flip-flop that is set when the count value of the counting circuit reaches the maximum count value and is reset by the reset signal, or The speed control device according to item 3. (5) The speed control device according to claim 1, wherein the counting circuit does not change the counted value after reaching the maximum counted value until the reset signal is input. (6) The speed control according to any one of claims 1 to 5, wherein the setting circuit includes another counting circuit that counts pulses whose phase is synchronized with the clock pulse. Device. (7) The speed control device according to claim 6, wherein the counting circuit and the other counting circuits of the setting circuit have the same maximum count value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984154787U JPS6170210U (en) | 1984-10-12 | 1984-10-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984154787U JPS6170210U (en) | 1984-10-12 | 1984-10-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6170210U true JPS6170210U (en) | 1986-05-14 |
Family
ID=30712780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984154787U Pending JPS6170210U (en) | 1984-10-12 | 1984-10-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6170210U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63127313A (en) * | 1986-11-18 | 1988-05-31 | Omron Tateisi Electronics Co | Counter |
-
1984
- 1984-10-12 JP JP1984154787U patent/JPS6170210U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63127313A (en) * | 1986-11-18 | 1988-05-31 | Omron Tateisi Electronics Co | Counter |
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