JPS63127313A - Counter - Google Patents

Abstract

PURPOSE:To obtain the result of speed detection at each count pulse input by comparing a clock number of an existing clock number count means with a referenced basic clock number and outputting a speed over signal based on the result of comparison. CONSTITUTION:A CPU 5 counts number C of basic clocks between count pulses P, P inputted from a rotary encoder 1 for every pulse P. Then the clock number C and the basic clock number B set by a RAM 8 in advance are compared, and when the clock number C is less than the clock number B and in case of C<B where the mobile speed of an object exceeds the highest counter speed, the CPU 5 outputs an overspeed signal V to an output line 9. On the other hand, in case of C>B, where the mobile speed is within the count permissible range, the CPU 5 turns off a signal V. Then the CPU 5 clears the speed counter and repeats the said operation sequentially. Thus, the count speed is calculated in a short time corresponding to a time between the pulses P, P and the result of speed detection is obtained at each count pulse input.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of the Invention The present invention relates to a counter that counts count pulses from, for example, a rotary encoder and outputs a control signal.

(b) Background of the Invention Conventionally, when moving a moving object in, for example, a N CijJ till system, if the moving speed of the moving object is too fast, the object may collide with a stopper and be damaged.

In order to solve such problems, conventionally, the moving speed of the above-mentioned moving object is detected by a rotary encoder, and the count pulses output from the rotary encoder are counted and a control signal is output. There is a counter that solves the problem.

This conventional counter outputs a counting control signal depending on how many count pulses P shown in Fig. 3 are input within a preset time T (specifically, about 1 second), so the counting speed is Since the above-mentioned set time T is always required for the calculation, there is a problem that stable data cannot be obtained for short poems due to the time required for this calculation. Since there is a time lag between the counter processing and the speed processing performed at predetermined time intervals preset in the ROM, there has been a problem in that real-time processing using speed data cannot be performed.

(c) Purpose of the Invention This invention is capable of obtaining speed detection results for each count pulse input, and can perform real-time processing using speed data, and furthermore, the object can be moved at a preset maximum speed. An object of the present invention is to provide a counter that can output an overspeed signal when the speed is exceeded.

(d) Structure of the Invention This invention comprises a clock oscillation means for periodically emitting a basic clock at a speed higher than the maximum counting speed, a current clock number counting means for counting the number of basic clocks between inputted count pulses, and a count pulse. a basic clock number setting means for setting a basic clock number serving as a reference between the two; a comparison means for comparing the clock number of the current clock number counting means with the clock number of the basic clock number setting means; Based on the above, the counter is characterized in that it is equipped with a control means for controlling the output of an overspeed signal when the current clock number is equal to or less than the number of locks i, S.

(E) Effect of the Invention According to this invention, the above-mentioned current clock number counting means counts the basic clock number transmitted between the count pulses from the low reencog or from the L cock transmitting means, and inputs the count pulse. Each time, the above-mentioned comparing means compares the clock number of the current clock number counting means and the clock number of the basic clock number setting means, which is a preset standard,
Based on the comparison result, the above-mentioned control means outputs an overspeed signal when the current clock number is less than or equal to the basic clock number.

(F) Effects of the Invention As a result, the counting speed can be calculated in a much shorter time than conventional methods, and the speed detection result can be obtained every time a count pulse is input.

Furthermore, since the result of speed detection can be obtained every time the count pulse is input as described above, there is an advantage that real-time processing using speed data can be performed.

In addition, when the moving speed of the object exceeds a preset maximum speed, the above-mentioned control means can output an overspeed signal.

(g) Examples of the invention An embodiment of the present invention will be described in detail below based on the drawings.

The drawing shows a counter, and in FIG. 1, two output lines 2.3 of a rotary encoder 1 which detect the moving speed and moving direction of a moving object and output count pulses P are shown.
A one-chip IC4 is connected to the terminal.

This IC4 has a CPU5 and an RO that stores programs.
M6, an input/output interface 7, and a RAM 8, and this RAM 8 stores target value A, current value a,
Necessary data such as the basic tarokk number B as a speed setting value is stored.

The above-mentioned Fukiri[-1tsukr11[3] is a preset value of the number of basic clocks b serving as a reference between the count pulses P and P shown in FIG. In this embodiment, for example, the number of basic clocks b is set to five to determine the number of basic clocks B serving as a reference.

In other words, the setting is such that when the basic clock b is 5 shots, the maximum moving speed of the object corresponds to within the allowable range.

Further, the CPU 5 described above periodically transmits the basic clock b at a speed higher than the maximum counting speed.

In other words, if the minimum period between the count pulses P and P shown in FIG. 3 is tl, and the period of the basic clock b is t2, then
The condition that satisfies the relational expression t2 < tl, or more specifically, t2 =
The basic clock b described above is transmitted under the condition of t115.

Further, the above-mentioned CPU 5 also receives input count pulses P,
The number of basic clocks b between P is counted every time a count pulse P is input.

Moreover, this CPU 5 compares the current clock number C between the above-mentioned count pulses P and P (see FIG. 2) with g<the current clock number B (see FIG. 2), and based on the comparison result, When C<B, overspeed signal V is sent to output line 9.
Output.

Furthermore, the above-mentioned IC4 has other host ICs such as CPU (
A data bus 10 and an address bus 11 are provided for connection to (not shown).

Further, the above-mentioned IC4 is provided with output lines 12, 13, and 14 that respectively output ON outputs when the relationship between the target value A and the current value a is A>a and A=a1A<a.

The operation of the counter configured in this way will be explained with reference to the flowchart shown in FIG.

In the initial state, the speed counter (specifically, the CPU built-in counter) that counts the number of clocks of the basic clock b is cleared, so for example, when one basic clock b is input at time t in FIG. 1st step 2
1, the CPU 5 increments (+1) the speed counter.

Next, in a second step 22, the CPU 5 outputs a count pulse P.
The presence or absence of input is determined, and since there is no count pulse P input at the above-mentioned time point to, the process moves to the next third step 23.

In this third step 23, the CPU 5 compares the current clock number C counted by the speed counter with the basic tally number B, and if C<B, returns to the first step 21,
At CA8, the process moves to the next fourth step 24.

- In this fourth step 24, the CPU 5 turns off the overspeed signal (2) on the output line 9, and then returns to the first step 21 described above. In other words, the fourth step 2 mentioned above
4, if the moving speed of the moving object is extremely slow, the overspeed signal @V is turned off without having a count pulse P input.
FF control.

While repeating the processing from the first step 21 to the fourth step 24, when the input point of the count pulse P is reached, in the second step 22 described above, the CPLJ 5 determines whether or not the count pulse P is input. Since there is a count pulse P input, the process moves to the next fifth step 25.

In this fifth step 25, the CPU 5 outputs the count pulse P
It is determined whether the direction of is +1 or -1. In other words, it is determined whether the moving direction of the moving object is the forward direction or the reverse direction, and when it is +1, the CPU 5 in the next sixth step 26 sets the current value a(
The CPU 5 increments (+1) the current value a (corresponding to the counting counter) in the RAM 8 (corresponding to the counting counter), while incrementing (+1) the current value a (corresponding to the counting counter) in the RAM 8 in another seventh step 27 when it is -1.

Next, in the eighth step 28, the CPLJ5 compares the target value A and the current value a, etc., and if A>a, in the next ninth step 29, the CPtJ5 outputs an ON signal to the output line 12, If A=a, in the next tenth step 30, CP
U5 outputs an ON signal to the output line 13, and if A<a, in the next eleventh step 31, the CPU 5 outputs an ON signal to the output line 14.

Next, in a twelfth step 32, the CPU 5 connects the output line 2.
Based on the count pulse P from 3, it is determined whether there is a change in the counting direction.

In other words, when the count pulse P shown by the solid line in FIG. If the direction is reversed, it is determined whether this direction has changed.

When the counting direction is reversed, for example from the positive direction to the reverse direction, a counting error will occur if the counting is continued F-.In order to eliminate this error, in the next 13th step 33, the CPU 5
clears the speed counter.

On the other hand, if there is no change in the counting direction, the process moves to the next fourteenth step 34.

In this 14th step 34, the CPU 5 uses the current clock number C (basic clock b, the gap between b [number of cocks]) and the RA
Compare the basic clock number B set in M8, and in case of CA8 where the current clock number C is less than the basic clock number B and the moving speed of the object exceeds the maximum counting speed, the following 15th
The process moves to step 35, and in this 15th step 35, C
PU5 outputs an overspeed signal V to output line 9.

On the other hand, in the fourteenth step 34 described above, the current clock number C
is greater than the basic clock number B and the moving speed of the object is within the counting tolerance range (C>B), the process moves to the next 16th step 36, and in this 16th step 36, CPtJ5 outputs the overspeed signal on the output line 9. Turn off V.

Next, in the thirteenth step 33, the CPU 5 clears the speed counter and prepares for counting between the next count pulses in FIG. .

To summarize as above, in the past, it takes time T to calculate the counting speed.
(See Figure 3), but in this embodiment, the counting speed can be calculated within a short time corresponding to the interval between the count pulses in Figure 2, and the speed detection results are calculated for each count pulse input. There is an effect that can be obtained.

As a result, it is possible to perform real-time processing using the speed data described above, which is extremely effective, for example, when performing NC control of a moving object.

In addition, when the moving speed of the object mentioned above exceeds the preset maximum speed, the above-mentioned CPtJ5 can output an overspeed signal to the output line 9. Appropriate control such as braking control can be performed.

In the correspondence between the configuration of the present invention and the above-described embodiments, the clock generation means of the present invention corresponds to the CPU 5 of the embodiment, and similarly, the current clock number counting means corresponds to the built-in counter of the CPU 5, The basic clock number setting means corresponds to a predetermined area of the RAM 8, and the comparison means corresponds to the third step 23 and the fourteenth step of the CPU 5.
Although the control means corresponds to step 3/l and the control means corresponds to CPLJ5, the present invention is not limited to the configuration of the above-described embodiment.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention; FIG. 1 is a block diagram of a control circuit for a counter, FIG. 2 is a flowchart, and FIG. 3 is a time chart. 5...CPtJ 8...RAMB...
・Basic clock number b...Basic clock C...Current number of clocks P...Count pulse Figure 2 flow chart Y-t

Claims (1)

[Claims] 1. Clock oscillation means for periodically emitting a basic clock at a speed higher than the maximum counting speed; current clock number counting means for counting the number of basic clocks between input count pulses; a basic clock number setting means for setting a reference basic clock number, a comparison means for comparing the clock number of the current clock number counting means and the clock number of the basic clock number setting means, based on the output of the comparison means. , and control means for controlling the output of an overspeed signal when the current clock number is less than or equal to the basic clock number.