SU1427334A1 - Device for controlling multicoordinate equipment - Google Patents

Abstract

The invention relates to a technique for numerical control of machine tools. The aim of the invention is to improve the performance of the equipment by reducing the output frequency. The device contains a computing unit — a computer 1, calculating (its multi-dimensional coordinate increment codes, communication channel 2, control unit 3, three coordinate channels 5,6,7, performing linear micro-interpolation increments, and channel 4 of the interpolation cycle time. The device allows you to programmatically change the cycle time of interpolation, which reduces the unevenness of the output pulses, reduces the limitations on the CNC machine feed rate and increases its productivity. 1 Cp f files, 7 ill. (L 4 to co oo 4 figure 1

Description

The invention relates to automation and computing and can be used in numerical control systems.

The purpose of the invention is to increase the equipment performance by reducing the output frequency.

Figure 1 shows the structural diagram of the proposed device; Fig. 2 is a control block diagram; FIG. 3 shows a divider circuit with a variable division factor; 4 is a frequency divider circuit; figure 5 is a diagram of the code converter; 6 and 7 are timing diagrams explaining the operation of the device as a whole and the frequency divider.

The multi-coordinate equipment control unit contains a computer unit 1 (computer) with communication channel 2, control unit 3, cycle time channel 4, three similar coordinate channels X, Y, respectively, 5.6, 7, buffer 8 and operating 9 cycle time, pulse generator 10, divider with variable division factor 11, buffer 12 and work 13 in each coordinate channel, coordinate increment registers, code converter 14 and frequency divider 15, in the computer unit 1 (computer). processor 16, random access memory (RAM) 17, permanent memory (ROM) 18, I / O control device 19, program input device 20, control device for console terminal 21, console terminal 22. The device also contains a reset line 23, a line timer 24, bus 25, communication lines 26, 27. Control unit 3 contains channel receivers 28, elements AND 29, 30, triggers 31, 32, 33, delay element 34, bus driver 35, decoder 36.- Divider variable division factor 11 contains the first 37 and second 38 counts pulses ki. Frequency divider 15 contains three elements And with inversion 39, 40, 41, counter 42, delay element on RC circuit 43, inverter 44. Code converter 14 consists of the first 45 and the second 46 pulse counters. The frequency divider 15 has inputs 47, 48.

The inputs of the buffer registers 8, 12 are connected by buses with data lines - ad

of the channel 2 of the computer 1, the outputs are connected to the inputs of the working registers 9, 13. The inputs of the code 14 converter are connected to the first outputs of the working coordinate registers 13. The first input of frequency divider 15 is connected to the output of the code 14 converter, and the outputs go to interpolator output: The first inputs of a divider with variable division factor 11 are connected to the outputs of the operating register of cycle time 9; the second input is connected to the output of generator 10. The output of the divider with variable division factor 11 is connected to code 14 converters of each terminal. ordinate channel. The outputs of the control unit are connected to the buffer registers 8, 12, and the inputs to the channel 2 of the computer 1.

The device works as follows i

After turning on the control unit of the multi-axis computer equipment G, a reset signal is generated, in which buffer 8, 12 and operating 9, 13 registers are reset, the program stored in ROM 18 is automatically started. Signals on the first outputs of code converters 14 and outputs of frequency dividers 15 are missing. At fixed intervals, a second start of the interpolation cycle is generated at the second output of the code 14 transducers. This signal on line 24 records information from the buffer registers 8, 12 to workers 9, 13, and also goes to channel 2 of the computer 1 to the timer line. Initially, interruption of the program of block 1 is prohibited and block 1 does not respond to a signal on the timer line.

According to the operator’s commands given from the console terminal 22, the NC control program is first entered. C. the input device of the program 20, its syntactic control is performed. Then the interpolation is started. Aborting the program is permitted. For each signal on line 24 (timer lines in channel 2) computer 1 loads the buffer registers 12 with multi-digit coordinate increments and the buffer register 8 with a multi-bit code that ultimately determines the signal output interval on the communication line 24-. Load values are calculated by computer 1 using linear algorithms or. circular interpolation with

multi-bit increments during the previous interpolation cycle. The contents of the buffer cycle time register change only to the end of the interpolation segment (interpolation frame) to reduce non-uniformity. Note also that by the signal on line 24, the information from the buffer registers 8, 12 will be rewritten to workers before the first ones from block 1 load. This is determined by the time delay in computer 1 to the interrupt signal along the timer line. Buffer registers 8, 12 are designed to be able to quickly load information from working registers 9, 12 during one clock of generator 10. The increments of coordinates from working registers 13 during a cycle t are converted into a unitary code by code converters 14. Frequency divider 15 reduces non-uniformity following the pulses during the interpolation cycle by dividing by four, and also switching their pulses to the output in positive or negative directions depending on the state of the most significant bit of the registers 13, direct and inverse outputs otorrhea connected to inputs 47, 48 are frequency dividers with Channels 15. Coordinate performed mikrointerpol linear increments tion on the basis of binary multipliers. However, the speed of microinterpolation will depend on two factors — the magnitude of the codes in the increment registers and the output frequency of the divider with a variable division factor of 11, which, at a constant generator frequency of 0, depends on the contents of the register 9. 6 and 7. For the sake of consistency, during the cycle time f, a divider with variable division factor 6 is generated. 32 pulses are generated, and the number 17 is stored in the working incremental coordinate register. s control unit. Channel receivers 28 are designed to amplify and invert channel signals. Element 29 takes 3-12 bits of the data address and the signal of the slave is an external device that is a logical combination of AND signals on lines 13-15 of the data address, is developed by block 1 and indicates what is happening appeal to the external device. For registers 8, 12, addresses 177760-177776 (octal numbers) are selected. When addressing these addresses in the address particles of the exchange cycle from block 1 to the D input of the trigger 31 is received 1. The signal POWER, produced by the central processor 16 when transmitting the address, records the fact that the device is sampled in the trigger 31, as well as the register address in the trigger 32, 33, During data transmission by the central processor, a signal is output, which, on condition of device sampling through element 30, delay element 34, pin driver 35 enters channel 2 of block 1 and confirms the sample, as well as decoding the decoder 36. Depending on On the one of the four output lines of the decoder 36, a signal appears that will be used to write data to one of the four buffer stations 8, 12. Delay element 34 is necessary for reliable recording of data from channel -2 Computer 1 in the buffer registers.

In FIG. 3, an example of implementation of a divider scheme with a variable division factor II is taken. It consists of serially connected counters 37 and 38. On line 26, the first counter receives pulses from the pulse generator 10, bus 27 is the code of the number N, which determines the output frequency on line 27. For each output pulse, a parallel code is written from the buffer register cycle times in counters 37 and 38

. "

on the bus 25. Therefore fp STT

"

where fr is the generator frequency.

Figure 4 shows a frequency divider circuit 15 containing AND elements with inversion 39-41, a counter 42, a delay element on a CS circuit 43 and an inverter 44. Frequency divider 15 divides the output frequency of the code converter 14 into four to reduce the unevenness, as well as distributes pulses to two channels depending on the sign of the increment. A feature of the scheme is that when the sign of the Increment of Information is changed, stored in the counter, it is not lost and is correctly processed. The line 49 receives signals from the converter code 14. If the increment is positive, then. on line. 47, -

M, and on line 48 - Oh, counter ra

is on summation, If the increment sign is negative, on line 47 - О, on line 48 - 1 and the counter works on subtraction. After issuing each pulse to output X or -X, counter 42 records the number of OD (eleven) into parallel recording mode. At the same time, at the outputs -X and tX - 1, at the input V of the counter 19 is also 1. With the arrival of the fourth pulse, level O turns on the line + X. After the delay time j determined by the RC circuit, the input V of the counter 42 receives the signal O setting the counter 42 to the state 1011. With a negative increment sign, the counter works on subtraction and with the arrival of the fourth pulse, the zero level appears on the -X line. The rest is similar to the previous case.

Let the main cycle time be selected and the code calculated that will be calculated when calculating increments according to the interpolation hormone. Block 1 -produces interpol with multi-digit increments, calculating the coordinate increments for the base cycle time, c.

Euler with linear interpolation:

2lL .. L

, Y--.

 -;

Xi- X; + ci.

c / z Hi4-i;

Thus, the output signals of the mouth

The features are transferred to the drives by the level Interpolation method has no significant 0. The operation of the circuit when the value changes is equal. For example, a good increment is shown by the diag- ramics given by the formulas in frame 6. In the proposed example, the sign change occurred at the moment when the number 42 was stored in the counter 42. In this case, the signal on the -X 30 line turns on only with the arrival of the fifth pulse, which is after the change of the increment sign. Thus, loss of information is excluded when the sign of the increment is changed. 35

Figure 5 shows a diagram of code converter 14. The circuit contains two counters 45 and 46. Line 27 receives pulses from a divider with a variable division factor 11. The output A1 of counter 46 during the cycle time shows the number of pulses specified by a code from the working register. These outputs are connected to frequency dividers.

15. On line 24, a 45 o signal appears (ji, OSU, S are calculated once a duty cycle every 4096 of the entire interpolation segment) of a frame of pulses, which is filled

4-1 - +0 (LjHt4;

Z 14 Z-1 + (Xz Vi i14,

where Hz ,, Y, Zy - coordinates of the end point;

L is the length of the segment of the interposition; about(); AY i-, i; o (y-H,

 AY, 4, o (z HL- - f AZif increments to the coordinates X, Y, Z; i - step number; H; .. - moving along the interpolation contour during the cycle T o Values

VII). Acceleration and deceleration is done by changing I.

operating registers and computer program 1 is terminated.

Coordinate channel registers are 13 bits. 1-12 bits - the increment of the coordinate in the forward code, connected with 0-11 bits of the address bus of the data channel 2 of the computer, 13 bits - the sign of the increment, connected with the 15 bits of the address data. The code converter 14 receives 12 code bits, the lower bits of the code being connected to the bottom lines.

in fig. 5, senior - with the top. The thirteenth bit of registers 13 (direct and inverse outputs) enters the inputs of frequency divider 15 via lines 47, 48. The cycle time registers are eight-bit, the inputs of buffer register B are connected to 0-7 address bus bits -. data channel 2 block 1. The time of the work chicle is determined by the formula

G 256 - Nf7

where N is the code in the working register of the cycle time 9;

fi- - chaitote generator 10.

Let the main cycle time be selected and the code calculated that will be calculated when calculating increments according to the interpolation hormone. Block 1 -produces interpol with multi-digit increments, calculating the coordinate increments for the base cycle time, c.

Euler with linear interpolation:

The interpolation method does not have a valid value. For example, good results are given by the formula

2lL .. L

, Y--.

 -;

Xi- X; + ci.

c / z Hi4-i;

Sobre interpolation has no su value. For example, ultata choir gives a calculation according to the form

the interpolation is not its value. For example, Ulta gives the calculation of p

4-1 - +0 (LjHt4;

Z 14 Z-1 + (Xz Vi i14,

o (ji, оСу, Ы are calculated once the entire interpolation segment) of the frame

where Hz ,, Y, Zy - coordinates of the end point;

L is the length of the interpolation segment; about(); AY i-, i; o (y-H,

 AY, 4, o (z HL- - f AZif increments of the coordinates X, Y, Z; i is the step number; H; .. - moving along the interpolation contour during the cycle T о

o (ji, оСу, Ы are calculated once the entire interpolation segment) of the frame

VII). Acceleration and deceleration is done by changing I.

For circular interpolation in plane, the algorithm with the alternation of the order of calculating the second order increments has a high accuracy, in which the following formulas are used for the odd steps:

 to to X (+ X

 Xf +

4-421111 V

+ Y,

4Yi., 40 (. YiH Yj- / JYi

t

LH. 4fi- Y, M, X /, X / +

+ 4X1 + 1, for even:

 -fli Y,., - A3 („

   t-f 1;

AXi.42 AO (i-b2Yt 2; +2 f + +

LU i, 2 D Hz; y.Q –UY, 4i,

where R is the radius of the interpolated circle, the asterisk indicates the auxiliary values that the computer does not carry into the microinterpolator;

Hi go

where and is speed;

 base cycle interpolation time.

The methodical error along the radius of the circular interpolation algorithm does not exceed the magnitude.

The control of the exit to the end point is performed on the maximum coordinate, DM MK - And, where Mc, is the final value of the maximum coordinate M - the current value of the maximum coordinate. The initial value of the maximum coordinate D M in the frame is taken equal to the equal value of the increment of the corresponding coordinate at the last interpolation step of the previous frame. If the difference between the final and current values of the maximum coordinate is less than 2DM, then this means that the last interpolation step in the frame will be calculated. Otherwise, calculations are performed using the linear interpolation algorithm. In this increment, the greatest coordinates will also be referred to as DMC. Increments and base code NO. The interpol tsy cycle time is produced by a signal on the timer line of a computer channel.

With circular interpolation, the control of exit to the end point is performed

0

five

0

five

P

5 5

0

five

along the contour. The value A is calculated - the distance from the current interpolation point to the end point. If A is less than the modulus of the doubled speed code H, then this means that the last frame step will be produced. Otherwise, the calculation is made using the interpolation algorithm and the timer is output by the signal. The value of A is calculated using the approximate formula: A / B, 38M with an accuracy of 4%. where B - corresponds to a coordinate, the difference between the current and final values of which is modulo larger than for another coordinate, which corresponds to the number M, i.e. always tm.

At the last interpolation step, for linear and circular interpolation, increments are computed to ensure accurate coordinates along the coordinates to the end point. At the same time, to reduce the jump in speed, it is calculated;

d

NK. , NK, NO yy where NO - base HK

cycle time code; HK is the speed code in the penultimate interpolation step.

With linear interpolation ADM, Ni. DM calculations for the maximum coordinate.

The degree of reduction in non-uniformity depends on the accuracy of the calculations and the size of the cycle time register. In this embodiment, the non-uniformity is reduced by a factor of 8-12.

In a device for controlling multi-axis equipment, it is easy to increase the number of controlled coordinates by adding the appropriate number of coordinate channels. In this case, the number of outputs of the control unit 3 must be increased accordingly, which is not difficult.

Formula of the invention

1. A device for controlling multi-axis equipment, containing a computing unit with a communication channel and a pulse generator, and in each coordinate channel - sequentially connected working coordinate increment register and code converter, characterized in that, in order to improve equipment performance by reducing output frequency into device

control block, buffer and operating cycle time registers, a divisor with a variable division factor, and a coordinate increment buffer register and a frequency divider, the first input: which is connected, are entered into each coordinate channel. With the first output, the transducer is connected to the bus the channel calculates the “block”, the first inputs of the buffer registers of each coordinate channel and the buffer register of the cycle time are connected by bus to the data lines — the channel address of the computing unit; the outputs of the buffer registers are the first inputs of the working registers of each coordinate channel, the first outputs of the code converters are connected to the first inputs of frequency dividers, the outputs of which are connected to the outputs of the device, the second and third outputs of the working registers are connected to the second and third inputs of the frequency dividers, respectively, the pulse generator is connected to the first input the divider with a variable division factor, the output of which is connected to the second inputs of the transducers of the codes of each coordinate channel, the second output of the transducer of codes o from the coordinate channels are connected to the second inputs of the working registers of each coordinate channel and the first inputs of the working cycle time register, as well as the timer line of the computational unit channel, the first output of the control unit is connected to the second input of the cycle time buffer register, the second, third and fourth outputs to the second entrances

the buffer registers of the coordinates of the first, second and third coordinate channels, respectively; the bus Reset the channel of the computing unit is connected to the third input of the buffer and to the second input of the working cycle time registers and to the third input of the registers of each coordinate channel; the outputs of the buffer register of Cycle time are connected to the third inputs 1and a working cycle time register, the outputs of which are connected to the second inputs of a divider with a variable division factor.

 about

2. The device according to claim 1, whether or not the frequency divider in each coordinate channel contains three elements And with inversion, g inverter, a pulse counter and an element of delay, and the first inputs of the first and second elements and with inversion are connected to the second and third outputs of the working register of the increment of the coordinates, respectively, the second inputs are connected to each other and to the output of the code converter, and the outputs of the first and second elements AND to the inversion are connected respectively to the first and second inputs of the pulse counter, the first and wto The swarm pulse counter outputs are connected to the first and second inputs of the third element And with inversion, respectively, and the device outputs, and the output is connected to the input of the e-node, the output of which is connected to the input of the inverter, the output of the inverter is connected to the input of the inverter, the output of the inverter is connected to the third input of the counter pulses.

/

D / DZ P3

t

 V

i 6

P + r

21

Phage

Signal

/ I ina h 5 Lini ffS

& La PP PP PP PP PP

15 .

 t

+ x

Frizni

Claims (2)

Claim 1. A device for controlling multi-coordinate equipment, comprising a computing unit with a communication channel and a pulse generator, and in each coordinate channel, a working register of coordinate increment and conversion 55 code shadow, characterized in that, in order to increase equipment performance by reducing the output frequency, a control unit, a buffer and a working cycle time register, a divider with a variable division coefficient, and a $ buffer register are entered into the device i O increments of the coordinate and frequency divider, the first input which is connected to the first output of the code converter, the control unit is connected by a bus to the channel of the computational unit, the first inputs of the buffer registers of each coordinate channel m and the buffer register of the cycle time are connected by a bus with data lines — the channel addresses of the computational 15 block, the outputs of the buffer registers are with the first inputs of the working registers of each coordinate channel, the first outputs of the code converters are connected with the first inputs of the dividers of the hour – 20 buffer registers of the coordinates of the first and second and the third coordinate channels, the bus Reset channel of the computing unit is connected to the third input of the buffer and to the second input of the working registers of the cycle time and to the third input of the registers azhdogo coordinate channel time buffer register outputs are connected to the third cycle of the working cycle time register inputs moves you are connected to second inputs of a divider with a variable division factor. * about 2. The device according to claim 1, it is distinguished by the fact that the frequency divider in each coordinate channel contains three AND elements with inversion, currents whose outputs are connected to the device outputs, the second and third outputs of the working registers are connected respectively with the second and third inputs of the frequency dividers, a central converter, a pulse counter and a delay element, the first inputs of the first and second elements AND inverting connected to the second and third outputs of the 25 working increment register, the pulse co-generator is connected to the first input of the divider the division coefficient, the output of which is connected to the second inputs of the code converters of each coordinate 3Q channel, the second output of the codes converter of one of the coordinate channels is connected to the second inputs of the working registers of each coordinate channel and to the first inputs of the working register of the cycle time, as well as with the timer channel line of the computational channel unit, the first output of the control unit is connected to the second input of the buffer register of the cycle time, the second, third and dd fourth outputs are to the second inputs of the dynat, respectively but, the second inputs are connected to each other and to the output of the code converter, and the outputs of the first and second elements And with inversion are connected respectively to the first and second inputs of the pulse counter, the first and second outputs of the pulse counter are connected to the first and second inputs of the third element And with inversion respectively, with the outputs of the device, and the output with the input of the delay element, the output of which is connected to the inverter input, the inverter output is connected to the inverter input, the inverter output · is connected to the third input of the pulse counter. FIG. 2 Fig. C. 1427334 Fig. C FIG. 5 • 1427334 Interrupt signal. \ ·. | line 24 - * ----------------------———-—----------------- L 1 2 3 4 5 61 8 9 10 11121514 1516111319 202122 23 / move bhoka ppppppppppppppppppppppppp tonaL 14 ____________________________________ Block / trunk of the unit ___ II --------- II II '1Г ~ - Fig. B Line 45 |. Line Ub ______________________ — _____ L_________________ 'ifenn PP P P Π Π · ..- Π-Β_.η..Πп s. ........... '~~ ..................... ₊ X Σ1ΕΖ — ΖΣΣ ^ .ΓΣΞΣ -Fig. 7