JPH03109177U

JPH03109177U -

Info

Publication number: JPH03109177U
Application number: JP1750890U
Authority: JP
Priority date: 1990-02-23
Filing date: 1990-02-23
Publication date: 1991-11-08

Description

[Brief explanation of drawings]

第１図は本考案の一実施例を示すブロツク図、
第２図は第１図の動作を示すタイムチヤート、第
３図は従来の一例を示すブロツク図、第４図は第
３図の動作を示すタイムチヤートである。１……アツプカウンタ、２……コンパレータ、
３……データ設定器、４……ピークホールド、５
……サンプルホールド、ａ……インデツクスパル
ス、ｂ……カウントパルス、ｃ……ピークリセツ
トパルス、ｄ……ホールドパルス、ｅ……イベン
ト信号、ｆ……ピークイベント信号、ｇ……ホー
ルドイベント信号、ｈ……カウントデータ信号、
ｉ……ピークリセツトデータ、ｊ……ホールドデ
ータ。 FIG. 1 is a block diagram showing an embodiment of the present invention.
2 is a time chart showing the operation of FIG. 1, FIG. 3 is a block diagram showing a conventional example, and FIG. 4 is a time chart showing the operation of FIG. 3. 1... Up counter, 2... Comparator,
3...Data setter, 4...Peak hold, 5
...Sample hold, a...Index pulse, b...Count pulse, c...Peak reset pulse, d...Hold pulse, e...Event signal, f...Peak event signal, g...Hold event signal , h...count data signal,
i...Peak reset data, j...Hold data.

Claims

[Scope of Claim for Utility Model Registration] A: An up counter whose count data is reset by an index pulse, counts the count pulses, and outputs a count data signal; B: A first data setter that sets peak reset data; C: The counter. A first comparator that compares the data signal and the peak reset data and outputs a peak reset pulse, D. A second data setter that sets hold data, E. Compares the count data signal and the hold data and outputs a hold pulse. a second comparator that outputs a peak event signal; F a peak hold whose output value is reset by the peak reset pulse and outputs a peak event signal by holding the peak of the event signal; A peak detection circuit comprising: a sample hold that outputs a hold event signal.