JPH0478821U - - Google Patents
Info
- Publication number
- JPH0478821U JPH0478821U JP12224390U JP12224390U JPH0478821U JP H0478821 U JPH0478821 U JP H0478821U JP 12224390 U JP12224390 U JP 12224390U JP 12224390 U JP12224390 U JP 12224390U JP H0478821 U JPH0478821 U JP H0478821U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- clock signal
- down counter
- coincidence
- detection means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Stereo-Broadcasting Methods (AREA)
- Control Of Amplification And Gain Control (AREA)
Description
第１図は、本考案の一実施例を示す回路図、第
２図は、従来のアツプダウンカウンタを備えたバ
ランス調整回路、第３図は第２図の計数回路２４
及びデコーダ２５の具体例、及び第４図イ乃至ト
は、第１図の説明に供する為の波形図である。
５３……アツプダウンカウンタ、５４……分周
回路、５５……レジスタ、６０……一致検出手段
、６７……計数回路。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a balance adjustment circuit equipped with a conventional up-down counter, and FIG. 3 is a counting circuit 24 of FIG.
and a specific example of the decoder 25, and FIGS. 4A and 4B are waveform diagrams for explaining FIG. 53... Up-down counter, 54... Frequency dividing circuit, 55... Register, 60... Coincidence detection means, 67... Counting circuit.
Claims (1)
て計数を行なうアツプダウンカウンタと、 前記クロツク信号源からの前記クロツク信号を
1/2分周する分周回路と、 該分周回路の出力信号をクロツクとして、前記
アツプダウンカウンタの出力データを取り込み、
保持するレジスタと、 前記アツプダウンカウンタの出力データと前記
レジスタの出力データとが一致することを検出す
る一致検出手段と、 該一致検出手段の検出出力信号を計数する計数
回路と、 から成ることを特徴とするロツク検出回路。 (2) 前記一致検出手段は、前記クロツク信号源
からのクロツク信号が印加されるゲート回路を備
えることを特徴とする請求項第１項記載のロツク
検出回路。[Claims for Utility Model Registration] (1) An up-down counter that performs counting according to a clock signal from a clock signal source;
A frequency dividing circuit that divides the frequency by 1/2, and using the output signal of the frequency dividing circuit as a clock, captures the output data of the up-down counter,
a register for holding, a coincidence detection means for detecting a coincidence between the output data of the up-down counter and the output data of the register, and a counting circuit for counting the detection output signal of the coincidence detection means. Features a lock detection circuit. (2) The lock detection circuit according to claim 1, wherein said coincidence detection means includes a gate circuit to which a clock signal from said clock signal source is applied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12224390U JPH0478821U (en) | 1990-11-20 | 1990-11-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12224390U JPH0478821U (en) | 1990-11-20 | 1990-11-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0478821U true JPH0478821U (en) | 1992-07-09 |
Family
ID=31870035
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12224390U Pending JPH0478821U (en) | 1990-11-20 | 1990-11-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0478821U (en) |
-
1990
- 1990-11-20 JP JP12224390U patent/JPH0478821U/ja active Pending
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