JPH01144884U - - Google Patents
Info
- Publication number
- JPH01144884U JPH01144884U JP4147388U JP4147388U JPH01144884U JP H01144884 U JPH01144884 U JP H01144884U JP 4147388 U JP4147388 U JP 4147388U JP 4147388 U JP4147388 U JP 4147388U JP H01144884 U JPH01144884 U JP H01144884U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- counted
- outputs
- random
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001629 suppression Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Description
第１図は本考案の一実施例のブロツク図、第２
図は本実施例の動作説明のためのタイミング図、
第３図及び第４図は本実施例の説明するための質
問パルス数に対する出力パルス数及び応答率を示
す相関図である。
００１…カウンタ、００２…計数値零検出器、
００３…ゲート回路、００４，００５…ＡＮＤ回
路、１０１…受信機、１０２…ランダム発生器、
１０３…受信抑圧ゲート、２０１…質問パルス、
２０２…ランダムパルス、２０３…出力パルス。
Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a timing diagram for explaining the operation of this embodiment.
FIGS. 3 and 4 are correlation diagrams showing the number of output pulses and response rate with respect to the number of interrogation pulses to explain this embodiment. 001... Counter, 002... Count value zero detector,
003...Gate circuit, 004,005...AND circuit, 101...Receiver, 102...Random generator,
103...Reception suppression gate, 201...Question pulse,
202...Random pulse, 203...Output pulse.
Claims (1)
ンダム発生器からのランダムパルスでカウントダ
ウンした計数値を出力するカウンタと、前記計数
値が零のとき前記ランダムパルスを出力し前記カ
ウンタのカウントダウンを禁止させるゲート回路
と、このゲート回路からの出力と前記質問パルス
との論理和を求めた出力のうち設定した受信禁止
時間よりも短い信号を抑圧する受信抑圧ゲートと
を有することを特徴とするパルス数制御回路。 A counter that outputs a counted value that is counted up by an interrogation pulse from a receiver and counted down by a random pulse from a random generator, and a gate circuit that outputs the random pulse when the counted value is zero and prohibits the counter from counting down. and a reception suppression gate for suppressing a signal shorter than a set reception prohibition time among the outputs obtained by calculating the logical sum of the output from the gate circuit and the interrogation pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4147388U JPH0648449Y2 (en) | 1988-03-28 | 1988-03-28 | Pulse number control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4147388U JPH0648449Y2 (en) | 1988-03-28 | 1988-03-28 | Pulse number control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01144884U true JPH01144884U (en) | 1989-10-04 |
| JPH0648449Y2 JPH0648449Y2 (en) | 1994-12-12 |
Family
ID=31267906
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4147388U Expired - Lifetime JPH0648449Y2 (en) | 1988-03-28 | 1988-03-28 | Pulse number control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0648449Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011185658A (en) * | 2010-03-05 | 2011-09-22 | Toshiba Corp | Distance measuring device and squitter generating method |
-
1988
- 1988-03-28 JP JP4147388U patent/JPH0648449Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011185658A (en) * | 2010-03-05 | 2011-09-22 | Toshiba Corp | Distance measuring device and squitter generating method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0648449Y2 (en) | 1994-12-12 |
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