SU1480118A1 - Reverse signal selector - Google Patents

Abstract

The invention relates to computing and digital measuring technology and can be used in the development of digital measuring equipment, as well as in various information processing systems. The purpose of the invention is to improve noise immunity and reliability. To achieve this goal, a decoder 1 and delay elements 2, 5, 6, 7 are entered into the device. The device also contains input buses 8, 9, AND-OR elements 3.4 and output buses 10, 11. The increase in noise immunity and reliability is due to the use of the dynamic principle of pulse generation and the absence of triggers. 2 Il.

Description

3 J 0-Н

j I

.eleven

,

t1

The invention relates to computing and digital measuring technology and can be used in the development of digital measuring equipment, as well as in various information processing systems using reversible counters.

The aim of the invention is to improve noise immunity and reliability. By eliminating the triggers and introducing the decoder and delay elements, which ensure the formation of pulses according to the dynamic principle.

FIG. 1 shows a block diagram of a device for extracting reverse signals; in fig. 2 - time diagrams of signals.

A device for extracting reverse signals contains (Fig. 1) a decoder 1, a first delay element 2, first and second elements H-OR 3 and 4, the second - fourth delay elements 5-7, the first and second input buses 8 and 9, and the first and second output tires 10 and 1.

Pa figs. 2 shows the timing diagrams of the signals Ugx ,, U0, U, U3, U1} UOJ, U fs, U3j, U4a, UWKiH U off respectively on the input buses 8 and 9, on the first, second, fourth, third outputs of the decoder 1 , at the outputs of the first, second, fourth, third elements 2, 5, 7, 6 delays and on the output tires 10, 11

The input buses 8 and 9 are connected respectively to the first and second inputs of the decoder 1, the first to fourth outputs of which are connected respectively to the inputs of the delay elements 2-7. The first and second inputs of the first structure AND element AND-OR 3 are connected respectively with the output element

2 delays and the second output of the decoder 1. The first and second inputs of the second structure AND of the AND-OR element 3 are connected respectively with the output of the element

5 delays and the fourth output of the decoder 1. The first n second inputs of the third structure And element I-III 3 are connected respectively to the output of element 7 delay and the third output of the decoder 1, the first and second inputs of the fourth structure And element I-ШШ

3 connected respectively with the first output of the decoder 1 and the output of the element 6 delay. The first and second inputs of the first structure AND element

AND-OR 4 are connected respectively to

five

80

 ...

,, -

20 25

30 35

40

118.2

the third output of the decoder 1 and the output of the element 2 delay. The first and second inputs of the second structure AND element AND-OR 4 are connected respectively to the output of delay element 6 and the fourth output of the decoder 1. The first and second inputs of the third structure AND element AND-OR 4 are connected respectively to the first output of the decoder 1 and the output of delay element 5. The first and second inputs of the fourth structure AND element AND-OR 4 are connected respectively with the second output of the decoder 1 and the output of the delay element 7. The outputs of the elements AND-OR 3 and 4 are connected respectively with the output tires 10 and 11.

Decoder 1 converts the binary code entering bus 8 and 9 into positional code, and when it arrives at spikes 8 and 9 of codes 00, 10, 01, and codes 1000, 0100, 0010 and, respectively, appear on the first to fourth outputs of decoder 1, respectively. 0001.

The device operates as follows.

Two variants of the relative change in the input signals UBh and UflXl over time (Fig. 2) arriving on buses 8 and 9 are possible.

In the first variant (Fig. 2, the section from the time t0 and t pЈb) each positive differential signal Ugx occurs at a low signal level U I, and each negative signal - at a high level signal UID2, and the time intervals

t "-t

one

t g, 3, t,

codes 00, 10, 11, 01 on the first and second inputs of the decoder 1 and high levels of signals U0, U1, U3, ig on its corresponding outputs correspond. At the same time, on the output of the element AND-OR 3 with the coincidence of the high levels of the signals U03 and UT, U 1a and U3, I3e and U4, U23 and U0, respectively, at time intervals Ts-t ,, t ± -t4, ta-fj, t4 -t, direct count pulses of a duration determined by the delay time of delay elements 2-7 are generated. At the output of the AND-OR element 4, the counting pulses are not generated, since the coincidence of high levels of U0 and 111z, U-, and U33, U3 and Uj3, Ui and 00j is not ensured

In the second variant (Fig. 2, the section from the time point tpe to the time point to) each positive

the signal drop U occurs when

high u signal

and each negative differential - with a low signal level Uexj, and the time intervals t5-t, ,, t-, tg-tq correspond to codes 01,, 00 on the first and second inputs of the decoder 1 and high levels of signals U5, U ,, Uf, U0 at its corresponding outputs.

At the same time, at the output of the element AND-OR 4 with the coincidence of the high levels of the signals of the Ai and U3, U,., And U ,, Utj and U0, U0. and Ut, respectively, on the time intervals tt-t /,, tg-t 9, tg-tg, counting pulses are generated with a duration determined by the delay times of elements 6, 7, 5, 2 delays, respectively. On the output of the AND-3 element, direct counting pulses are not generated, since no high levels of the signals U0j and V.1t U and U3, U3 and U4j- and U0 are ensured.

The proposed device, compared with the prototype, despite the simplicity of implementation, has significant noise immunity and reliability, which allows to obtain high reliability of information, including with rapid irregular code changes, which is achieved by using fewer logical elements, as well as because the proposed device relates to devices of the dynamic type (it responds to the front of the input signals, and in the prototype the conversion is performed according to the level of the signals). In the proposed device, the process of forming a counting pulse lasts a very short time interval, which makes it possible to significantly increase the noise immunity.

Claims (1)

Invention Formula A device for extracting reverse signals, containing two input buses, two output buses, and two AND-OR elements, each of which contains a ler and a second structure AND, ot t -Q j Q 5 0 o five five 0 L and so that, in order to improve noise immunity and reliability, a decoder and four delay elements are entered into it, and in each AND-OR element - the third and fourth structures AND, the first and second input buses are connected to the first and second inputs of the decoder, respectively the first, second, third and fourth outputs of which are connected respectively to the inputs of the first, second, third and fourth delay elements, the first and second inputs of the first AND structure of the first OR element are connected respectively with the output of the first element beyond holder and the second output of the decoder, the first and second inputs of the second structure AND the first element AND-OR are connected respectively to the output of the second delay element and the fourth output of the decoder, the first and second inputs of the third structure AND the first element AND-OR are connected respectively to the output of the fourth delay element and the third output of the decoder, the first and second inputs of the fourth structure AND the first element AND-OR are connected respectively to the first output of the decoder and the output of the third delay element, the first and second inputs n And the second element AND-OR is connected respectively to the third output of the decoder and the output of the first delay element, the first and second inputs of the second structure AND the second element are connected respectively to the output of the third delay element and the fourth output of the decoder, the first and second inputs of the third, second structure element AND-OR connected respectively with the first output of the decoder and the output of the second delay element, the first and second inputs of the fourth structure AND the second element AND-OR are connected respectively with the second output of the decoder and the output of the fourth delay element, the outputs of the first and second elements AND-OR are connected respectively with the first and second output pshni. tpee t5tj tgtg ijt f tgt g tst s Phage. 2