SU594501A1 - Comparator - Google Patents

Description

(54) COMPARATOR

P is a binary-decimal number equal to the upper limit of the measured value.

The measured value in the form of a binary-decimal number can be entered into the comparator either in parallel or in a sequence TejsbHOM code. In the case of parallel input, the generator of 5 clock signals starts operating, which generates pulses, the number of which during the comparison cycle is equal to the maximum possible total "decade bit weight of the counter, i.e. n fifteen (1 + 2 + 4 + 8-15): First impulse directly enters the combined inputs of the elements And the first bits of each group 4, the second and third pulses arrive at the combined inputs of the elements AND the second bits of each group 4 through the element OR 7, the fourth to the seventh pulses arrive at the combined inputs of the elements And tr the three bits of each group 4 through the element OR 8, the pulses from the eighth to the fifteenth arrive at the combined inputs of the elements AND the fourth bits of each group 4 through the element OR 9. Thus, the number of pulses at the output of the group of elements OR the panel “weight the corresponding bit yes of the decade of measurable value. The clock pulses pass only through the elements of the measured number opened by the resolving potentials of the AND elements to the common inputs of binary part 1 counters 1 and 2. The code of the measured number is recorded in the counters. Due to the combination of the inputs of the And elements in the same-named bits of each group 4 of the measured number, the flow of pulses occurs simultaneously in all a decade of binary-decimal counters I and 2, in which writing is allowed.

In order for the transfer of a logical unit, caused by the previous pulse of the clock signal generation, to occur before entering the binary-decimal counters, an alternate pulse, the speed of the clock signal generator 5 is one order less than the speed of the triggers on which binary-decimal counters 1 and 2.

Binary-decimal counter 1 overflows under the condition of A – f – C — K C, i.e., with A A,

where A is the measured value, represented by the binary-ten code.

The i-decade counter 2 overflows with, with the condition A + C -, i.e.

When the binary-decimal counter 1 overflows and the binary-decimal counter 2 is incomplete, threshold element 3 generates a signal “NORM, if both counters overflow, the signal is“ MORE NORMAL, and if both counters are not filled, “LESS THAN NORM.

In the case when the measured value

represented in sequential code, entering it

via bus 11 through the common entrance

The first decade of binary-decimal counters.

I and 2.

The generator of clock signals, the group of elements AND 4 and the elements OR 7, 8 and 9 are not involved in the work.

The number of parallel-connected binary digits 1 and 2 may be more than two. In this case, the functionality of the comparator will be broader. He will be able to give signals that the measured values are no longer in one of the three intervals (A4K; AR), but in one of four or more, for example, K AitP; P A "5Q; A Q, where).

In comparison with the known in the proposed comparator, instead of the four n-pulse formers of medium complexity, the use is 35 (herewith only three OR logic elements. The proposed simpler execution of the comparator reduced the duration of the comparison cycle, since it has a generator speed

the clock signals, which determine the speed of the entire device, should be an order of magnitude smaller than the speed of the trigger of decades of counters, rather than two orders of magnitude, as in a known device. This slowed down clock speed generator is due to the fact that in order to maintain the efficiency of the whole comparator, the fifth, ninth, thirteenth, and in general {4m + 1) -th pulse at the output of the generator can appear only after Eight pulses from the output of the corresponding driver, caused by the fourth, eighth, twelfth, and generally 4th pulses of this generator (a ti-tural number). Consequently, the duration of the period T of pulses of the clock generator in the proposed comparator is 5-10 times

0 is less than the duration of the period T of pulses of the clock generator in the known device. The duration of the comparison cycle in the proposed comparator is T 15 T, in the well-known tu, 4n.T.

Claims (2)

1. USSR author's certificate No. 444) 80 55 cl. G 06 G 7/04, 11.08.72. 2.Avtorskoe svi l telc.tvy USSR № 37564 cells; G 06 F 7/04, 04.01.71. hi t No IEJ trLJ h R P ± J " -H