SU1319262A1 - Device for delaying pulses - Google Patents

Abstract

The invention can be used in measuring and computing. The purpose of the invention is to improve the accuracy of the delay. The device contains a generator 1 counting pulses, the elements And 2 and 4, counters 3 and 5 pulses, the element 6 comparison, form, or 7 single pulses, the inverter 8 and the driver of single pulses. The introduction of the element And 9, the decoder 10, the element 11 of the delay and operational memory devices 13 and 14 reduces the dynamic error of the delay time when changing the code time delay. 1 il.

Description

The invention relates to a pulsed pulse AND 4. In the counter 3 pulses of the apparatus and the number defining the value of CGl can be used.

measuring and computing technology. the previous pulse. With this element b

The purpose of the invention is to increase the point-of-comparison fixes the coincidence of numbers

the delay due to the reduction of the dynamically recorded delayed pulses in the RAM 14 and in the counter 3, and the output of the element 6 as the delay time code changes. There is a zero potential blocking

The drawing shows a block diagram of the device element AND 2. The element 9 of the closed impulse delay effect. The left potential coming from the input bus 15.

The device delay pulses content- 0 When appearing on the input bus 15

there is a series-connected positive impulse device across Petor 1 counting pulses, element II 2 on the middle front, driver 12 forms 3 counts of pulses, sequentially connects a single short pulse, which

The first element 4, the first input of which sets the pulse counter 3 to the output of the generator 1, counts from the left position and records the code of the known pulses, and the pulse counter 5, connected in series to the comparison element 6, the output of which is connected directly to the second input of the And 2 and through the shaper 7 single pulses Sz from the input code buses 16-1, ..., 16-p to RAM 14. Element I 2 opens and from the generator output 1 counting pulses with a period of (), where T, Symp the period of and duration - with permission input The settings of the input pulses are 20 pulses, the inverter 8 and the counting input of counter 3. The simultaneous AND 9, the output of which is connected to the summing input of the counter of 5 pulses, the decoder 10, whose inputs are connected to the outputs of the counter of 5 pulses, and the output connected to the second input element And 4, the element 11 of the delay, the input of which is connected to the output of the generator 1 counting pulses, and the output from the third input element And 9, the driver 12

25

but with this, the signal of the logical unit from the output of the comparison element 6 via the inverter 8 keeps the AND 9 element in the closed state. Pulse counter 5 does not change its state.

If tKMn 4: 3; T, then at the moment of the end of the input pulse, its trailing edge records in the RAM 13 the number M, accumulated in the counter 3 during the time timp.

single pulses, the output of which is under- OQ. Thus, in RAM 13 is recorded directly to the zeroing input of the counter 3 pulses, the first random access memory (RAM) 13, the outputs of which are connected to the installation inputs of the pulse counter 5 and the second random access memory (RAM) 14, the recording input of which is combined with the zeroing input of the 3-pulse counter. The input bus 1.5 is connected to the input of the shaper 12 single pulses, the recording input of the operational storage device 13 and the second 35

Timp rank, measured in Tc units. At the end of the pulse on the input bus 15, the counter 3 continues to count the pulses coming from the generator output. 1, until the number accumulated in the counter 3 coincides with the number recorded in the RAM 14. When these numbers coincide, the output of the comparison element 6 appears zero potential, the locking element AND 2, which leads to the counting of pulses by the counter 3. Simultaneously With this form input element I 9. The outputs of the rectifier 40 generates a single pulse, the pulse of 3 pulses is connected to the information which permits rewriting from RAM 13

in the counter 5 pulses of the number M. In this case, at the output of the decipheror 10, a single potential appears, opening

memory inputs 13 and with the first inputs of the corresponding bits of the comparison element 6, the second inputs of the respective., And 4, through which the counting digits of the comparison element 6 are connected to the pulses from the generator 1 output

with input code buses 16-1, ..., to the subtracting input of counter 5. At 16-n via RAM 14. From the output bus to the subtracting input of the counter 5 M th

17 is connected to the output of the decipheror 10. The output of the counting pulse counter 5 sets the element AND 4 is connected to the input of the calculator in the zero position and at the output

The pulse counter 5, which 50 of the Decoder 10 appears to be zero potential, is reversible. The locking element is AND 4. The device operates as follows.

In the initial state (before a delayed pulse arrives at the input busbar 15) the pulse counter 5 is in the zero state, and at the output of the decoder 55 of the torus 10, which records the zero state of the pulse counter 5, there is a zero potential that covers the element on the output bus 15 a pulse of duration, timp and delayed by ts, is formed. When the element And 9 is always in the closed state.

If ts; timp, then the process of counting pulses by the counter 3 stops before the end of the input pulse on the input bus 15. In this case, when the position is positive, it writes the code of the value Cz from the input code buses 16-1, ..., 16-p to RAM 14. Element And 2 opens and from the generator output 1 counting pulses with a period of the next (), where T, Symp the period of the next and

but with this, the signal of the logical unit from the output of the comparison element 6 via the inverter 8 keeps the AND 9 element in the closed state. Pulse counter 5 does not change its state.

If tKMn 4: 3; T, then at the moment of the end of the input pulse, its trailing edge records in the RAM 13 the number M, accumulated in the counter 3 during the time timp.

Thus, in RAM 13 is recorded great. Thus in RAM 13 is written down

Timp rank, measured in Tc units. At the end of the pulse on the input bus 15, the counter 3 continues to count the pulses coming from the generator output. 1, until the number accumulated in the counter 3 coincides with the number recorded in the RAM 14. When these numbers coincide, the output of the comparison element 6 appears zero potential, the locking element AND 2, which leads to the counting of pulses by the counter 3. Simultaneously with this, shaper 7 generates a single pulse that permits rewriting from RAM 13

is the unit potential opening

 element 4, through which the counting pulses from the output of generator 1 enter

The decoder 10 appears a zero potential, the locking element And 4. Thus, on the output bus 15, a pulse of the duration timp and delayed by m3 is formed. When the element And 9 is always in the closed state.

If ts; timp, then the pulse counting process by the counter 3 stops before the end of the input pulse on the input bus 15. In this case, when the potential of the output element 6 compares two numbers is two, the former 7 generates a single pulse and writes to counter 5 through the open RAM 13 the number N accumulated by the counter 3 and determining the value of h. Thereby, at the output of the decoder 10, a single potential is formed,

opening element AND 4. The unit potential present at the output of the inverter 8 and the input pulse on the input bus 15 open the element 9, through which the delayed counting pulses arrive at the summing input of the counter 5. Until the end of the pulse on the input bus 15 to the subtracting and summing the inputs of counter 5 are synchronized, but counting pulses delayed relative to each other, i.e., the number N - (- 1, then N is alternately recorded in the counter. For this, the delay time of the delay element 11 of delay element 11 must be within TT + TS: hh p Tc-tt-TS, where tg is the duration of the counting pulses, T5 is the total response time of the counter 5 and the decoder 10. Choose the most efficient. Thus, counter 5 records the number N by the end of the pulse on the input bus 15. After the end the pulse on the input bus 15, the element And 9 is closed and the counter 5 starts to work only for subtraction. Upon the arrival of the Nth counter pulse from the moment the output pulse ends, the counter 5 is set to the B zero state and the output of the decoder 10 shows a zero potential nt and 4. Thus is generated on output line 17 pulse is delayed by a duration TK and TIMI.

Claims (1)

Invention Formula A pulse delay device containing a series-connected counting pulse generator, the first And element and the first pulse counter, the second And element in series, the first input of which is connected to the output of the gene0 five 0 five 0 five 0 Ratio counting imp.: 1 сон son, and the second pulse point, the first and inopoii single formers, 1 С C (H5 and NPNe 1tor, characterized in that, with k.chk), due to the accuracy and delay, by reducing the dynamic error of the delay time when changing time delay code, a comparison element is entered into it, the output of which is connected to the inputs of the inverter and the second single pulse generator and the second input of the first element I, the first random access memory, whose information inputs are combined with the first inputs corresponding to the bit elements of the comparison of two numbers and connected to the corresponding bit outputs of the first pulse counter, Brojioe (operational storage device, den1if ()) () | 1, whose inputs are connected to the ra: p bottom of the second output of the second counter and and the output is connected to the second VTO1O1CH1 The I element and the successively connected delay element, the input of which is connected to the generator is distinct, 1x pulses, and the third element I, the second input of which is combined with the input of the first operational storage ycTpoAcTiui and the input of the first formati.h single imp. The switch is connected to the input niniioii, and the output is connected to the second input; L in the impulse counter, the installation inputs of which are connected to the outputs of the first operational memory ycTiioiicTBa. the output of the first form, 1 single pulses, is connected to the zeroing input of the first counter. The input of the second single pulse generator is connected to the enable input of the second counter, uNnn .ibcoB, the output of the inverter is connected to the third input of the third element, And the output of the generator is connected with output C) uiniioi t, and the second inputs of the corresponding bits of the E.C. comparison are connected to the input code buses through a second random access memory, the recording input of which is 1 ×) with (connected with the output of the first form) nrovate.ch single pulses.