SU1064450A1 - Signal-duration selector - Google Patents

Abstract

SELECTOR SIGNALS ON DURATION, containing a pulse counter, a decoder, the inputs of which are connected to the outputs of the bits of the pulse counter, a pulse generator, the first output of which is connected to the R input of the pulse counter, the second output to the gate input of the decoder, the first element I, the first input of which connected to the output of the older bit of the pulse counter of the second, third, and fourth elements of AND, the first inputs of which are combined, and the output of the first two of which are connected respectively to the first and second output buses, n n The second and sixth AND elements, characterized in that, in order to extend the functional capabilities by providing the possibility of obtaining information on the presence of a potential signal at the input and on its duration, two triggers are introduced into it, the OR element and the pulse shaper, whose input is connected to the input bus and the first input of the second element And the output to the second input of the first element And the first input of the fifth element And R and the input of the first trigger, the output of which is connected to the third output bus and the second inputs of the second and The third element I, 5 is an input to the output of the encoder dei and the first input of the sixth element I, the second input of which (L C is connected to the fourth output bus and the forward output of the second trigger, the inverse output of which is connected to the second input of the fifth element I, 5 -input - with the first input of the first element And,; R -input - with the output of the sixth element And the second input of the fourth element And, the output of which is connected to the first input of the OR element, the second input of which is connected to the output of the fifth element And, the output to p the output bus, and the output of the first element I is connected to the counting input of the pulse counter, and then the first inputs of the first and third elements I are inverse.

Description

The invention relates to a pulse technique and can be used in automatic monitoring and control devices. A device is known that contains two pulse counters, two decoders for a torus, a pulse shaper, a pulse generator, and an And l element. The disadvantage of the device is low functionality, since it cannot determine the presence of a potential signal at its input and its duration. The closest in technical essence to the present invention is a pulse selector containing, a pulse counter, a counting input which is connected to the input bus, the decoded inputs of which are connected to the outputs of the bits of the pulse counter, the pulse generator, the first output of which is connected to the R-input of the counter pulses, the second output is to the gate input of the decoder, the control input is to the first output of the decoder, the block of elements I, the first inputs of which are combined and connected to the second output of the decoder, and the second inputs are connected from responsibly to the outputs of the bits of the pulse counter, the pulse generator consists of a clock pulse generator, the output of which is connected to the first input of the element I, the second input of which is the control input, and the output connected to the counting input of the pulse counter, which output The delay element is connected to its R input, the outputs of the delay element of the pulse generator are respectively the first and second outputs of the pulse generator 2. A disadvantage of the known devices is also low functionality, since it cannot determine the presence of a potential signal at the input and its duration. The purpose of the invention is to enhance the functionality by enabling information on the presence of a potential signal at the input and its duration. The goal is achieved by the fact that in the signal selector on. length, containing a pulse counter, a decoder, the inputs of which are connected to the outputs of the pulses of the pulse counter, the pulse generator whose first output is connected to the R input of the pulse counter, the second output to the gate input of the decoder, the first element I, the first input of which connected to the output of the higher bit of the pulse counter of the second, third and fourth elements of AND, the first inputs of which are combined, and the outputs of the first two of which are connected respectively to the first and second output buses, fifth and sixth elements of AND, VV There are two triggers, an OR element and a pulse shaper, the input of which is connected to the input bus and the first input of the second element AND, the output to the second input of the first element AND, the first input of the fifth element AND and R - the input of the first trigger, the output of which is connected to the third the output bus and the second inputs of the second and third elements I, the 5 input to the output of the decoder and the first input of the sixth element I, the second input of which is connected to the fourth output bus to the forward output of the second trigger, the inverse output of which is connected to the second input n m And, S is the input with the first input of the first element and the R input with the output of the sixth element AND and the second input of the fourth element AND whose output is connected to the first input of the OR element, the second input of which is connected to the output of the fifth element AND the output is to the fifth output bus, the output of the first element AND is connected to the counting input of the pulse counter, and the first inputs of the first and third elements AND are inverse. Figure 1 shows the functional diagram of the selector signals for the duration; 2 shows time diagrams. The signal selector contains a pulse counter 1, a decoder 2, a generator of 3 pulses, a driver of 4 pulses, the first 5 and second 6 triggers, six AND 7-12 elements, respectively, an OR 13 element, an input 14 and five output 15 to 19 buses, respectively. In the signal selector to the input bus 14 are connected the first inputs of the elements And 8-10 and the input of the imaging device 4, the output of which is connected to the second input of the element And 7, R - input of the trigger 5 and the first input of the element And 11. The counting input of the counter 1 is connected to the output of the element And 7, and the outputs of its bits - with the inputs of the decoder 2. First, the output of the generator 3 is connected to the R input of the counter 1, the second output to the gate input of the decoder 2, the output of which is connected to the 5 input of the trigger 5 12. The output of the trigger 5 is connected to the bus 17 and the second inputs element in And 8 and 9, the outputs of which are connected to buses 15 and 16.5 — the input of trigger 6 is connected to the first (input) input of element I 7 and the output of the high bit of counter 1, the R input of trigger 6 is connected to the output of JjOM element 12 and the second input element AND 10, the output of which is connected to the first input of the element OR 13 The forward output of trigger b is connected to the second input of the element 12 and the bus is. The inverse output of the trigger 6 is connected to the second input of the element 11, the output of which is connected to the second input of the element OR 13. The output of the element OR 13 is connected to the bus 19 As the decoder 2 can use the multi-input element And, and the inputs of which are inverse 1) -th entrance - Pr my.

The selector signal duration works as follows.

The former 4 selects the leading edge of the input signal. The generator 3 at the outputs Sj and S generates a repeating sequence of a pair of short, shifted relative to each other and not coincident in time, pulse (Fig. 28), and at the output 5-2 pulses appear earlier; than output 5.

In the absence of a signal selector input, counter 1 is reset by pulse S to zero, its outputs (junior and senior rar) are no signsshov, and decoder 2 impulses 52 at the output a pulse that flips trigger 5 into one state.

When a potential signal is received at the input of the selector (Fig. 2a) in the same way, the trigger 5 is switched to a single state (Fig. 2b). This occurs after the second pair of pulses S and 5 {(Fig. 2S), since the first pair of pulses drops counter 1 to the zero state. Earlier, a low signal existed at the output of the low bit of counter 8 as a result of the occurrence of a pulse at the output of shaper 4 due to the last edge of the potential signal. Thus, in the absence (for a period of time greater than the interval between the pairs of gating pulses) changes in the state of the input of the selector on the unit output of the trigger 5, a logical signal is generated.

When a pulse sequence with a period of at least several times smaller than the period of gating pairs arrives at the selector input, the output signals are not only output at the low-order but also at the output of the high-order bit (ft counter 1).

The first pulse at the input of the selector trigger 5 is reset to the 10th left state, and the pulses, starting with the t1 pulse (in the interval between the gating pairs), are blocked by a signal at the output of the high discharge of counter 1. At the same time, the signal 5 from the output of the high discharge of the counter Figure 1 translates into a single state trigger b, signaling the presence of a series of pulsed signals at the selector input (Fig. 2d).

Q After the termination of a series of pulse signals, regardless of whether there is a pause or a potential signal appears, signals are collected at both inputs of the And 12 element, which ensure the firing of its output and reset of trigger b to the zero state. If a series of pulsed signals are replaced by potential, signals, signals for a certain time are present at both inputs of the element AND 10 and at the output of the OR element (Fig. 2) a pulse signal appears at the beginning of the potential signal at the selector input. The beginning of a series of short pulses after pause 5 is also accompanied by the appearance of

pulse signal at the output of the element OR 13, since at the output of the element 11 there is a pulse signal.

The signals on buses 15 and 16 (Figures 2o 0 and g) allow the duration of the potential signals and pauses to be estimated accordingly.

The proposed selector, in comparison with the known one, possesses enhanced functional capabilities due to the formation of separate signals at separate outputs, which allow controllers. not only the presence at the input of the pulse sequence and its beginning, but also the presence of a potential 0 at the input

social signal and its duration, as well as the duration of the pause.

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Claims (1)

DURATION OF SIGNALS OF DURATION, containing a pulse counter, a decoder, the inputs of which are connected to the outputs of the bits of the pulse counter, a pulse generator, the first output of which is connected to the R-input of the pulse counter, the second output to the gate input of the decoder, the first element And, the first input of which is connected with the high-order output of the pulse counter, the second, third and fourth AND elements, the first inputs of which are combined, and the output of the first two of which are connected respectively to the first and second output buses, the fifth and the second oh elements AND, characterized in that in order to expand the functionality by providing the possibility of obtaining information about the presence of a potential signal at the input and its duration, two triggers are introduced into it, an OR element and a pulse shaper, the input of which is connected to the input bus and the first input of the second element And, the output - to the second input of the first element And, the first input of the fifth element And and R-input of the first trigger, the output of which is connected to the third output bus and second inputs of the second and third element Comrade I, 5th input - to the output of the decoder and the first input of the sixth § element And, the second input of which is connected to the fourth output bus and the direct output of the second trigger, the inverse output of which is connected to the second input of the fifth element And, the 5th input - with the first input the first element And, R input - with the output of the sixth element And and the second input of the fourth element And, the output of which is connected to the first input of the OR element, the second input of which is connected to the output of the fifth element And, the output to the fifth output bus, and the output of the first element And connected to the counting at the entrance of the pulse counter, and the first inputs of the first and third AND elements are inverse. SU „„ 1064450