SU1739492A1 - Device for separating first and latest pulses in train - Google Patents

Abstract

SUMMARY OF THE INVENTION: The device comprises shapers 1, 19 pulses, counters 2 and 3 pulses, decoders 4 and 5, shift registers 6 and 7, delay elements 8 and 9, coincidence elements 10 and 11, trigger 12, OR element 13, clock generator 14 pulses, inverter 15, output buses 16 and 17, input bus 18 with corresponding connections. 1 il.

Description

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The invention relates to telecommunications and can be used in devices for processing pulse signals of control systems, telecontrol, and telemetry.

A device for isolating the first and last pulses in a series, comprising output buses, two D-triggers, the D input of the first of which is connected to the common bus, and a delay element whose input is connected to the input bus are known.

The disadvantages of the known device are the limited range of durations and periods of the pulses under study and the impossibility of the device operating with variable parameters of the pulses in series.

The closest in technical essence to the present invention is a device for separating the first and last pulses in a series, containing two D-flip-flops, two output buses, the D-input of the first flip-flop is connected to a common bus, a delay element whose input is connected to an input bus , a reset bus, two NAND elements, and two OR elements, the output of the first of which is connected to the first output bus, the first input - to the first input of the second OR element, with the direct output of the second D-flip-flop, and the first input of the first AND element -NO, the second input - with inverse the output of the first D-flip-flop and the second input of the first NAND element, and the third input - with the output of the delay element, the C-input of the first D-flip-flop and the second input of the second OR element, the output of which is connected to the second output bus, and the third input - the direct output of the first D-flip-flop, S- input of which is connected to the input bus and the first input of the second NAND element, the second input of which is connected to the output of the first NID element, and the output - with the C-input of the second D-flip-flop, D whose input is connected to its inverse output, and the R input is connected to the reset bus.

A disadvantage of the known device is a narrow range of temporal characteristics of the processed pulses within the series, since the device is operational provided that Tmax m 2 Tmin where Tmin is the minimum follow-up period of the input pulses, t is the delay time, Tmax is the maximum follow-up period. In this case, the following condition must be met: 2Tmax Tmax, otherwise the device is inoperable.

The purpose of the invention is to expand the range of values of the periods of the processed pulse series.

The goal is achieved by the fact that, in a device for selecting the first and last pulses in a series, containing a trigger, an OR element, a first and a second match element, a first delay element, the input of which is connected to the input

bus, the first and second output bus, entered the first and second shift registers, clock generator, the second delay element, the first and second pulse counters, the first and second decoders,

the first and second pulse shapers, an inverter, the input of the first pulse shaper is connected to the input bus, and through an inverter with the input of the second pulse shaper, the output is from the counting

the input of the first pulse counter, with the first input of the element. OR with the reset input of the second pulse counter, the counting input of which is connected to the output of the pulse generator and with the information inputs of the first and second shift registers, the outputs with the corresponding inputs of the first decoder, the output of which is connected with the first input of the first match element, with the R input of the trigger and with the input

reset the first pulse counter, the outputs of which are connected to the corresponding inputs of the second decoder, the output of which is connected to the second input of the first element of the match, the output of which

connected to the second input of the OR element and the reset input of the second shift register, the output of which is connected to the first output bus, information input through the second delay element to the output of the second coincidence element, the first input of which is connected to the inverse trigger output, the second input to the input of the first element delay, the output of which is connected to the information input of the first register

shift, the reset output of which is connected to the output of the OR element, the output is connected to the second output bus, and the S input of the trigger is connected to the output of the second pulse generator.

The drawing shows a block diagram of the device.

A device for isolating the first and last pulses in a series contains the first pulse shaper 1, the second pulse counter 2, the first 3 pulse counters, the first 4 and second 5 decoders, the first 6 and second 7 shift registers, the first 8 and second 9 delay elements, the second

10 and the first 11 elements of coincidence, trigger 12, element OR 13, clock generator 14, inverter 15, first 16 and second 17 output buses, input bus 18, second pulse shaper 19.

In addition, the device may include a second inverter 20.

The output of the imaging unit 1 is connected to the inputs of blocks 3, 2 and 13. The outputs of block 2 are connected to the inputs of the decoder 4, the outputs of the block are the 3rd inputs of the decoder 5, the output of block 4 is connected to the corresponding inputs of blocks 3 and 11 and to the R input of the trigger 12, the output of block 5 is connected to another input of element 11, the outputs of registers 6 and 7 are connected to output buses 17 and 16 of the device, respectively, the outputs of delay elements 8 and 9 are connected respectively to information inputs of registers 6 and 7, the output of coincidence element 10 is connected to input element 9 delay, the output element 11 Connected to the inputs of blocks 7 and 13. The inverse output of the trigger 12 is connected to the input of the element 10. The output of the element 13 is connected to the corresponding input of the block 6. The output of the generator 14 is connected to the counting input of the block 2 and to the synchronous inputs of registers 6 and 7. The output of the inverter 15 is connected to the input of the block 19. The input bus 18 is connected to the combined inputs of blocks 1, 8, 10 and 15. The output of block 19 is connected to the S- input of the trigger 12. It is possible that the combined inputs of blocks 1, 8, 10 and 15 are connected to the bus 18 via an inverter 20.

The device works as follows.

When the interval between pulses is greater than the maximum period of pulses in a series, the device makes a decision about the end of a series. After that, the first pulse can be selected as the first pulse of the next series. The next pulses, the intervals between which do not exceed the maximum specified pulse period, are intermediate pulses of this series; the last is a pulse, after which during the time interval, longer than the maximum period, no next pulse arrives.

In the presence of element 20 (the second inverter), negative pulses are extracted, without this element, positive pulses occur.

In the initial state, trigger 12 is in the zero state, the counters and registers are zero (the initial installation chains are not shown).

Bus 18 to the input of the device receives a series of pulses. The first incoming pulse of the series arrives at delay element 8, shaper 1, where a short pulse is generated along the leading positive front of the input pulse.

positive polarity, which passes through the OR element 13 to the reset input of the register 6. The delay element 8 is necessary so that when a pulse arrives at the device input, the register 6 is first reset, and then the pulse is recorded in the register 6. The delay element 9 is needed for compensation of the delay element 8 in order to ensure that the first impulse of the series and the last impulse of the series are not distorted by the duration and delay of one relative to another.

The pulse generated by shaper 1 on the leading edge of the input pulse also enters the reset of counter 2, which then starts counting the clock pulses, starting from the zero state. The pulse from the imaging unit 1 also increments the state of the counter 3. The counters 2 and 3 calculate, respectively, the period of the next pulse of the series and the number of pulses in the series.

The input pulse through delay elements 8 and 9 goes to registers 6 and 7, which are controlled delay elements that work as follows: these are shift registers. The shear pulses come to them from generator 14, advance information on registers 6 and / Number of adjacent bits in registers that contain units proportional to the duration of the next impulse of the series, NI Tj / Tr, where r, the duration of the i-ro impulse of the series, and Tr is the period of the pulses following from generator 14. The controllability of registers as delay elements consists in the fact that at any time the register can be reset (cleared). The delay time of registers 6 and 7 must satisfy the condition of the TG hTmax, i.e. - greater than the maximum value of the period of the pulses in the series, which corresponds, unlike the known device, to the presence of only a lower limit for the period of the pulses in the series.

On the trailing edge of the first pulse of the series (at this moment the positive potential is removed from the output of the inverter 15), the shaper 19 is triggered, a short pulse from the output of which trigger 12 is set to one, which prevents the rest of the pulse from passing through the AND 10 element (coincidence element) at the input of the register 7.

Thus, after a time equal to the delay time, the first pulse of the series is output from the output of the register 7 to the output bus 16. At the output of register 6, this pulse does not appear, because, in accordance with the condition Tmax Tz, the contents of register 6 are zeroed at the leading edge of the second pulse of the series (similarly, each subsequent pulse of the series drops its register 6 through its driver 1). At the same time, each subsequent impulse of the series resets the first counter with the same signal from the former 1 and increments the contents of the second counter 3. With the falling front, each impulse of the series confirms the single state of trigger 12.

This continues until the last pulse of the series. The decoder 4 is configured so that at its output a positive signal appears when counter 2 reaches the content corresponding to the maximum period of the pulse in the series. The signal from the decoder enters the input of element 11 and analyzes the contents of counter 3. This is necessary to exclude single pulses from a series of sequences that, as in the known device, are considered interference and are excluded from the input sequences.

The pulse from the decoder 4 resets the trigger 12, allowing the arrival of a new series of pulses for processing, and the counter 3, after which the device is ready for processing the next series of pulses.

At the same time, since there is no signal to reset the register 6, a positive pulse is formed from its output on bus 17, equal in duration to the last pulse of the series.

Thus, on tires 16 and 17, the first and last pulses of each series are extracted, respectively. In this case, the device functions correctly irrespective of the minimum value of the pulse following periods within the series.

When a single (interfering) pulse arrives at the input (since this pulse is both the first and the last pulse of the fictitious series), it transfers counter 3 to state 1. Counter 3 remains in this state until the decoder 4 triggers. A decoder 5 tuned to the unit content of counter 3 generates a positive potential, and a positive pulse goes through the element OR 13 to the input of register 6, as well as to the input of register 7, resetting both registers to the zero state, preventing the formation of pulses on the output tires of the device.

Thus, the proposed device allows to significantly expand the range of parameters of the processed pulse series, practically removing the restrictions on both the ratio of the minimum and maximum periods of the pulses in the series, and their absolute values.

Claims (1)

Apparatus of the invention for separating the first and last pulses in a series, comprising a trigger, an OR element, a first and a second coincidence element, a first delay element, whose input is connected to the input bus, the first and second output buses, characterized in that in order to extend the range values of the periods of the processed pulse series, the first and second shift registers, the clock generator, the second delay element, the first and second pulse counters, the first and second decoders, the first and the second pulse formers, an inverter, the input of the first pulse generator is connected to the input bus and through an inverter with the input of the second pulse shaper, the output is connected to the counting input of the first pulse counter, to the first input of the OR element and to the reset input of the second pulse counter, the counting input of which is connected with the output of the pulse generator and with the information inputs of the first and second shift registers, the outputs with the corresponding inputs of the first decoder, the output of which is connected to the first input of the first element match, with the R input of the trigger and the reset input of the first pulse counter, the outputs of which are connected to the corresponding inputs of the second decoder, the output of which is connected to the second input of the first match element, the output of which is connected to the second input of the OR element, and to the reset input of the second shift register, the output of which is connected to the first output bus, the information input through the second delay element to the output of the second coincidence element, the first input of which is connected to the inverse output of the trigger, the second input to the input ne The delay element, the output of which is connected to the information input of the first shift register, the reset input of which is connected to the output of the OR element, the output is connected to the second output bus, and the S input of the trigger is connected to the output of the second pulse former.