SU1566474A1 - Device for monitoring sequence of pulse signal alternation - Google Patents

Abstract

The invention can be used, in particular, to control the sequence of alternation of pulse signals. The goal is to expand the functional capabilities of the device by allowing the control of the minimum permissible pause time between pulses and the elimination of the limitation on the pulse width of the pulse former. This is achieved by introducing adjustable elements 17.1-17 into the device (N-1). / N-1 / delay and additional forcing 18 pulses. The device also contains N input buses 5.1-5N, a driver of 8 pulses, elements 11 and 12, triggers 2.1-2N of the first group, / N-1 / triggers 3. 1-3. (N-1) of the second group, element And / AND-NOT 4, N triggers 7.1-7. N of the third group, (N-1) flip-flops 9.1-9./N-1/ of the fourth group, the element OR 10, the bus 13 "continue monitoring", R _S- trigger 14, the bus 15 "failure" and the multi-way element OR 16. 1 il.

Description

The invention relates to a pulse technique and can be used in control systems, processing and formation of pulse signals.

The purpose of the invention is the expansion of functionality by providing the ability to control the minimum allowable pause between pulses and eliminate restrictions on the duration of the pulse jq pulse shaper.

The drawing shows an electrical functional diagram of the device.

A device for monitoring the sequence of alternating pulse signals contains η two-input elements And 1.1 - 1.η, η triggers 2.1-2.p of the first group, (p-1), triggers Z.1.-

3. (p-1) of the second group, the element AND / AND-NOT

4, η input buses 5.1-5.P, (p-1) elements And 6.1-6. (P-1) with a different number of inputs, n flip-flops 7.17. In the third group, the first driver 8 pulses (p-1 ) triggers 25 9.! - 9. (n-1) of the fourth group, an OR element. 10, first 11 and second 1'2 elements AND, bus 13 Continue monitoring, RS-flip-flop 14, bus 15 Failure, multi-input element OR 16, (p-1) 3 adjustable elements 17.1-17. (P-1) delays, the second driver 18 pulses, and the outputs of the two-input elements And 1.1-1.η are connected to the S inputs of the corresponding RS-flip-flops 7.1-7.η of the third group, the first inputs - with the outputs of the corresponding triggers 2.1-2.P. the first group, the corresponding inputs of the element AND / AND NOT 4 and the inputs of the corresponding regulated elements 17.1 -1 7. (p-1) delays, second inputs - with * corresponding input buses 5.1-5 .η, clock inputs of the corresponding triggers 2.1-2, p of the first group, and starting from the second input of the second two-input element And 1 .2, - with S- by the inputs of the corresponding triggers 3.1-3. (p-1) of the second group, the S-input of trigger 3. (p-1) is connected to the input of the first driver _(for 8 pulses, R-inputs of RS-triggers

3.1-3. (P-1) of the second group are connected to the R-inputs of triggers 2.1-2.η of the first group, triggers 7.1-7, η of the third group, triggers 9.1-9. (P-1) of the fourth, fourth group and with the output of the element OR 10, and the inverse outputs of the triggers I

3.1- 3. (p-1) - with inputs of AND elements

6.1-6. (N-Ί) with a different number of inputs, and the inverse outputs of triggers 3.K-3 are connected to the inputs of the Kth element AND 6.K. (η-I) from K to (p-1) -th, another input of each of the elements AND 6.1-6. (p-1) with a different number of inputs is connected to the output of the corresponding adjustable element 17.1-17. (p -1) delays, and the outputs of the elements And 6.1-6. (P-1) with a different number of inputs are connected to the S-inputs of the corresponding triggers 9.1-9. (p-1) of the fourth group, the outputs of which are connected to the corresponding input of the AND / AND-NOT 4 element, whose inverse output is connected to the first input of the first And 11 element, and the direct output - to the first input of the second And 12 element, the output of which is connected to the input of the second pulse shaper 18, and the second input with the output of the first Shaper 8 pulses and the second input of the first element And 11, the output of which is connected to the input of the multi-input element OR 16, the remaining inputs of which are connected to the outputs of the corresponding triggers 7. 1-7.η of the third group , and exit - with the S-input of the RS-flip-flop 14, the output of which is connected to the bus 15 Failure, and the R-input - with the bus 13 Continue monitoring with the first input of the OR element 10, the second input of which is connected to the output of the second pulse shaper 18.

The device operates as follows.

In the initial state, all memory devices are driven by a signal from the bus 13 'Continue monitoring, while at the outputs of triggers 2.1-2.P, RS triggers 7.1-7.η of the third group, RS triggers 9.1-9. (P-1) of the fourth group and RS- trigger 14 - zero signals on the inverse output of RS-flip-flops

3.1-3. (P-1) of the second group - single signals.

Consider the operation of the device with the correct alternation of input pulse signals. The pulse signal from the first bus 5.1 is fed to the second input of the two-input element And 1.1 and the second input of the trigger 2.1, at the output of which a single signal is set at the rear Front of this signal, which is fed to the input of the AND / AND-NOT 4 element. through an adjustable delay element 17.1 at the input of the first element AND 6.1. Since on the other inputs of the And 6.1 element there are single signals from the outputs of the corresponding RS-triggers 3.1-

3. (p-1), then the output element And

6.1 a single signal appears, on the leading edge of which the RS-trigger

9.1 of the fourth group will be set to a single state. The pulse signal from the first bus does not pass to the output of the two-input element And 1.1 and, therefore, the S-input of the RS flip-flop 7.1 of the third group, since the resolving single signal at the first input of the two-input element And 1.1 appears with the output of trigger 2.1 only along the trailing edge of the pulse signal with 5.1 tires

With the correct sequential alternation of signals on the input buses 5.2-5.η, the pulse signal from the corresponding bus 5.2-5.η is fed to the second input of the corresponding element And 1.2-1.p, the clock input of the corresponding trigger 2.2-2.η and Sinput of the corresponding RS- trigger

3.1-3. (P-1) of the second group. In this case, on the front Front of the input pulse signal at the inverse output of the corresponding RS-trigger 3.2-3. (N ~ 1) of the second group, and on the rear Front of the input pulse signal at the output of the corresponding clocked trigger 2.2-2.η, zero and single signals are formed, respectively . A single signal from the output of the corresponding clock trigger 2.2-

2.η arrives at the corresponding input of the AND / AND-NOT 4 element, through the corresponding adjustable element 17.2-17. (P-1) of the delay - to the input of the corresponding element 6.2-6. (P-1), at the other inputs of which moment there are single signals from the outputs of the corresponding RS-triggers 3. 2-3. (η- 1) of the second group. Therefore, the output of the corresponding element And 6.2-6. (p-1) a single signal will appear, on the leading edge of which the corresponding RS-trigger 9.2-9. (p-1) of the fourth group is set to a single state.

Zero signals at the inverted outputs of RS-triggers 3.1-3. (P-1) of the second group, if the pulse signals are correctly alternated on the input buses 5.1-5.η, do not affect the further operation of the device.

The output of the corresponding two-input element AND 1.2-1.p and, therefore, the S-input of the corresponding RS trigger 7.2-7.η of the third group, the pulse signal from the corresponding input bus 5.2-5.η does not pass, since the resolving unit signal at the first input of the corresponding the two-input element And 1.2-1.p appears from the output of the corresponding clocked trigger 2.2-2.η only on the trailing edge of the pulse signal from the corresponding input bus 5.2-

5.p. As a result, after the correct arrival of all pulse signals at the output of all clocked triggers 2.1-2.P, all RS-triggers 9.19. (P-1) of the fourth group and, therefore, all inputs and direct output of the I / I-BE 4 element, are single signals, and at the output of all RS triggers

7.1-7.η of the third group, the inverse output of the AND / AND-NOT 4 element and the output of the OR 16 element are zero signals. Therefore, at the output of the RS-flip-flop 14 and the output bus 15, there is no “Failure” signal, and the pulse signal generated at the output of the first Shaper 8 pulses with a delay relative to the rear Front of the ηth pulse signal passes through the And 12 element to the input of the second shaper 18 pulses . At the output of the last input signal on the trailing edge, a pulse signal is generated, which, through the OR element 10, enters the R-inputs of the triggers and sets the device to its initial state. When two pulse signals arrive at any of the input buses 5.1-5.η instead of one, the device generates an alternation order violation signal on the output bus 15 as follows.

The pulse signal, which appeared a second time on the input bus 5.1-5.y>, is fed to the second input of the corresponding two-input element And 1.11 .p, at the first input of which there is already a single resolution signal from the output of the corresponding clocked trigger 2.1-2.P. Therefore, the second signal from the input bus 5.1—

5.η passes to the output of the corresponding two-input element AND 1.11 .p, enters the S-input of the corresponding RS-flip-flop 7.1-7.η of the third group and sets the output signal to it, which through the corresponding input of the multi-input element OR 16 goes to S- RS trigger input 14. As a result, an RS signal is generated at the output of the RS trigger 14 and the output bus 15.

In the absence of a pulse signal or the presence of a constant signal on one of the input buses 5.1-5. (P-1) at the output of the corresponding clocked trigger 2.1-2. (η-l) No single signal is generated. As a result, at the direct and inverse outputs of the AND / AND-NOT 4 element, there are zero and single signals, respectively. Therefore, the pulse signal generated at the output of the first driver 8 pulses with a delay relative to the trailing edge of the n-th pulse signal through the element And 11 and the multi-input element OR 16 is fed to the S-input of the RS-trigger 14. At the output of the RS-trigger 14 and the output bus 15 generates a Fault signal.

In the absence of the ηth pulse signal or its constant level at the output of the ηth clock trigger 2.η, a single signal does not appear, and a pulse signal is not generated at the output of the first pulse shaper 8, which ensures the formation of the Failure signal on the output bus 15. However, after the first pulse signal is received from the input bus 5.1 on the output bus 15, a Failure signal is generated as if an extra pulse signal was received.

In case of violation of the order or time of alternation of pulse signals, the formation of the signal Failure on the output bus 15 occurs as follows. The pulse signal received through the input bus 5.K (2 <K <n) with a violation of the order or time of the alternation of signals sets the leading signal at the inverse output of the RS-flip-flop 3. (K-1) zero signal. Since the zero signal at the output of the corresponding elements And 6.1-6. (K-1) It is formed earlier than at the outputs of re. walkable elements 17.1-17. K (1 <i <Kl) there are single signals from the outputs of the clocked triggers 2.i2. (K-1), formed on the trailing edge of the pulses from the corresponding input buses 5.i-5. (K-1 ), then it blocks the passage of the incoming stream of single signals from the outputs of the adjustable elements 17. i-17. (K-1) delays through the corresponding elements AND 6.ϊ-6. (Κ-1) to the S-inputs of the corresponding RS-triggers 9.i-9. (K-l) of the fourth group. Therefore, at the outputs of RS-flip-flops 9.ϊ-9. (Κ-1), even after the arrival of all input pulse signals, zero signals.

As a result, at the direct and inverse outputs of the multi-input AND / INE 4 element, there are zero and single signals, respectively. A pulse signal generated at the output of the pulse shaper 8 with a delay relative to the trailing edge of the η-th pulse signal is supplied to the S-input of the RS-flip-flop 14 through the element 11 and the multi-input element OR 16 at the output of the RS-trigger 14 and the output bus 15. In the absence of the ηth pulse signal or its constant level, a single signal does not appear at the output of the ηth trigger trigger 2.η, and a pulse signal is not generated at the output of the pulse shaper 8, which generates a Failure on the output bus signal. However, after the first pulse signal is received from the input bus 5.1 on the output bus 15, a Failure signal is generated as if an extra signal were received.

Monitoring the status of the outputs of the clocked triggers 2.1-2.P, RS-triggers 7.1-7.P, 9.1-9. (η-l) of the third and fourth groups, respectively, it is possible to accurately determine the nature of the failure.

Thus, the proposed device allows you to control not only the sequence of alternating input pulse signals, but also the minimum time interval between the trailing and leading edges of two adjacent pulses, as well as determine the specific cause of the failure.

Claims (1)

Claim A device for monitoring the sequence of alternating pulse signals containing η input buses, the ηth of which is connected through a pulse former to the first inputs of the first and second elements And, all η input buses are connected to the first inputs of the first group of η elements And, respectively, with C inputs the first group of η triggers, respectively, and. ΙΟ starting from the second input bus, connected to the S-inputs of the second, groups of p-1 triggers, respectively, the R-inputs of which are connected to the R-inputs of the first '$ group η triggers, R-inputs of the third group and triggers, R-inputs of the fourth group p-1 triggers and the output of the first OR element, and inverse outputs - with the corresponding inputs of the second group of p-1 elements AND with a different number of inputs, and the inputs of the K-th element of this group are connected to the inverse outputs of the triggers from K to (n-1) th, respectively, 15 but, the outputs of the elements AND of the second group are connected to the corresponding S-inputs of the fourth group of p-1 flip-flops, the outputs of which are connected to the corresponding inputs of the AND / AND-NOT element, the direct and inverse outputs of which are connected to the second inputs of the first and second elements AND, and the remaining inputs are connected to the corresponding outputs of the first groups η of triggers and with second 25 inputs of the first group of η AND elements, respectively, the outputs of which are connected to the corresponding S-inputs of η triggers of the third group, whose outputs are connected to the corresponding inputs of the second OR element, (n + 1) -th input of which is connected inen with the output of the first AND element, and the output with the S-input of the first trigger, the output of which is connected to the output bus, and the R-input is connected to the bus' Continue monitoring with the first go of the first OR element, characterized in that, in order to expand the Functional opportunities by providing the ability to control the minimum allowable pause between pulses and eliminate restrictions on the pulse duration at the output of the Pulse former, it introduced η-I adjustable delay elements and an additional pulse former, whose input is is dined with the output of the second AND element, and the output with the second input of the first OR element, the inputs of the delay elements are connected to the corresponding outputs η of the triggers of the first group, and the outputs with the corresponding inputs of p-1 elements AND with a different number of inputs of the second group.