RU1803967C - Pulse generator - Google Patents

Abstract

The invention relates to pulsed technology and can be used in automation and computing devices. The device contains: 3 elements I-N E (1,6,10), 1 bus of clock pulses (2), 1 bus of control (3), 3 triggers (4,5,6), 1 element of I (12), 3 output buses (7, 8, 9). 3 ill.

Description

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The invention relates to pulse technology and can be used in automation and computer systems, in particular in information receiving and processing devices.

An object of the invention is to extend the frequency range.

Figure 1 shows a diagram of a device; Figures 2 and 3 are timing diagrams explaining the principle of operation of the claimed device and prototype, respectively.

The pulse shaper contains the first AND-NOT 1 element, the first input of which is connected to the clock bus 2, the second input to the control bus 3, the third input to the inverse output of the second trigger 4, and the output to the C-input of the first trigger 5, pr my output is connected to the first input of the second AND-NOT 6 element, the output of which is the first output bus 7, the inverse output of the first trigger 5 is connected to the C-input of the second trigger 4 and the second output bus 8, the third output bus 9 connected to the output third element AND NOT 10, the first input is cat it is connected to the direct output of the third trigger 11, the second input to the C-input of the third trigger 11 and to the output of the And 12 element, the first, second and third inputs of which are connected to the corresponding inputs of the first And-NOT 1 element, the output of which is connected to the second the input of the second element. AND NOT 6.

The device operates as follows.

In the initial state, the zero signal level on the control bus 3 (Fig. 2b) locks the NAND AND 1 and 12 elements on the second input and holds the triggers 4, 5, 11 in the zero state. At the same time, AND-NOT elements 6, 10 are blocked by logic zero signals from the direct outputs of triggers 5 and 11 (Figs. 2d, g), respectively. When a single level is applied to the bus 3 (Fig. 26) after the time of the signal and 1I, corresponding to the propagation delay time of the signal in the AND-NOT 1 and AND 12 elements, the clock signals present on the bus 2 at the outputs of these elements are formed inverted — on (FIG. 2 c) and direct (FIG. 2 e) a sequence of clock pulses. On the leading edge of the inverted and falling edge of the forward sequence, triggers 5 and 11 respectively fire. After a time tT corresponding to the propagation delay of the signal in the trigger, single signals are generated at the direct outputs of triggers 5 and 11 (Fig. 2d, g). permitting the passage of pulses so

output frequencies to the outputs of AND-NOT elements 6 and 10. The following clock pulses, allocated by elements 1 and 12 (figv, e) set the triggers 5 and 11 to the state

logical zero (Fig. 2d, g). As a result, negative pulses of half-gates are generated at the outputs of elements b and 10, (Fig. 2e, h), of duration rci fi and tC2 r-i, respectively, where t and ta, respectively

the duration of the positive and negative half-cycles of the clock frequency. When using a clock signal type meander bg. On the inverse output of the trigger 5 connected to the bus 8,

a positive pulse is generated with a duration T equal to the period of the clock frequency, on the leading edge of which the trigger 4 is activated (Fig. 2i). By the signal from the inverted output of trigger 4, the elements INE 1 and I 12 are blocked at the first input, the supply of clock signals to the C inputs of triggers 5 and 11 is stopped. When a potential of zero potential appears on the control bus, trigger 4 is set to a logic zero state, and triggers 5 and 11 are maintained in this state and the circuit goes into standby mode for the next control signal.

All circuit elements can be performed on integrated circuits (ICs). For example, the I-NOT 1 element - on the IMS K155LA4, the I-NOT 6 and 10 elements - on the IMS K155LAZ, the I-12 element on the IMS K555LIZ, triggers 4 and 5 - on the IMS K155TV15, the trigger

and -aIMSK155TV6.

In the prototype device (3), upon receipt, a control signal (Fig. 36) from clock pulses (Fig. 3a) by the second circuit

AND-NOT 6 after a tn-not time corresponding to the propagation delay of the signal in the AND-NOT element, an inverted sequence of clock pulses is generated (Fig. Sv). With duration

positive and negative half-cycles of the clock frequency corresponding to the speed of triggers 1, 2, 8, an error occurs in the prototype circuit in the formation of the pulse width of the half-gate,

associated with a positive half cycle of the clock signal. Indeed, along the leading edge of the signal generated by the element IN-E 6 (Fig. Sv), after a time rm corresponding to the propagation delay of the signal in the trigger, a signal is visible at the direct output of trigger 1 (Fig. Sg), the leading edge of which is delayed relative to the leading edge of the clock pulse at the time 1i-not. As a result, the AND-NOT 3 element

a half-gate pulse will be formed, with the duration Гс1 Ги-not, where - the duration of the positive clock pulse. On the trailing edge of the pulse emitted by the element И-Н Е 6, the trigger 8 will fire with a delay tT (Fig. Зе) and a half-gate pulse (Fig. ЗЖ) will be generated with the element И-НЕ 7, where тг is the duration of the negative half-cycle of the clock frequency . Thus, in the prototype device, the half-gate pulse duration associated with the positive half-cycle of the clock frequency is formed with an error equal to tn-not. The proposed technical solution allows to eliminate the specified error and, as a result, to expand the frequency range of the device used.

Claims (1)

SUMMARY OF THE INVENTION A pulse shaper comprising a first AND-NOT element, the first input of which is connected to the clock bus, the second input to the control bus and the R inputs of the first, second, third triggers, and the output to the C-input of the first trigger, my direct output is connected to the first input the second AND-NOT element, the output of which is connected to the first output bus, the inverse output of the first trigger is connected to the second output bus and the C-input of the second trigger, whose inverse output is connected to the third input of the first AND-NOT element, the direct output of the third trigger connected to the first input of the third AND-NOT element, the output of which is connected to the third output bus, the second input to C-input of the third trigger, characterized in that, in order to expand the frequency range, an element And, the output of which is connected to the C-input of the third trigger, the first, second and the third inputs are with the corresponding inputs of the first AND-NOT element, the output of which is connected to the second input of the second AND-NOT element. 91 / g. B