SU1718368A1 - Pulse generator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices. The purpose of the invention is the extension of functionality due to the formation of both a single pulse and a sequence of pulses of undistorted duration - achieved by introducing an additional D-trigger 6 and element AND 3. The device also contains a D-trigger 1, a delay element 2 consisting of an even number series-connected inverters 2-1 ... 2-p. 2 Il.

Description

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The invention relates to a pulse technique, in particular to a pulse shaper, and can be used in automation and computing devices.

A pulse shaping device is known which contains a trigger and a first NAND element, the first input of which is connected to the control bus, and the output is connected to the S-trigger input, the second AND-NOT element, the first input of which is connected to the inverse output of the trigger, the second input with the C-flip-flop output, and a clock pulse bus, and the output is the output of the pulse shaper and is connected to the second input of the first AND-NOT element, with the control bus connected to the D-flip-flop input.

The known device uses a separate generator of a continuous sequence of pulses (not shown) and a scheme for linking pulses to the control signal of a temporary gate.

However, the device does not provide for the formation of a series of pulses necessary, for example, to control two-fold shift registers. The reliability of the formation of the last pulse of the series is not ensured if the inhibit signal arrives at the control input at the time of the formation of the pulse. As a result, a single pulse formation mode (one-shot mode) necessary for, for example, controlling the shift register in the start-stop mode,

These drawbacks of the device are due to the fact that in its operation there is asynchrony between the clock pulses and the control signal, which can reach the period of clock pulses.

The closest to the invention is a pulse shaper on a D-flip-flop, the C-input of which is connected to a source of control signals, and the inverse output of a flip-flop - with its D-input and through 2n series connected elements NOT, with the R-input of the O-flip-flop

However, at the outputs of the device, only one pulse is generated in response to a control signal and, therefore, this device cannot ensure the formation of a sequence of pulses.

In addition, the driver has an increased sensitivity to impulse noise, since the inverse output of the D-flip-flop is connected to its D-input, then when a pulsed disturbance occurs at the control input of the device, at the moment

the formation of a pulse, a false trigger will occur, i.e. there will be a distortion of the duration of the formed pulse sequence.

The purpose of the invention is to enhance the functionality by forming both a single pulse and a sequence of pulses of undistorted duration.

0 The goal is achieved by the fact that a pulse shaper containing a D-flip-flop, the inverse output of which is connected to the output bus, and through a delay element consisting of an even number of 5 therefore connected inverters is connected to its R-input, the control bus is additionally introduced, the bus mode of operation, an additional D trigger and an AND element whose output

0 is connected to the C-input of the D-flip-flop, the first input is with the output of the delay element, the second is connected to the control bus and to the R-input of the additional D-flip-flop, the D-input of which is connected to the control bus of the operating mode, C-input - with output bus, and inverse output with D-input D-flip-flop. FIG. 1 shows a functional diagram of a pulse former; in fig. 2 - time diagram of his work.

0 The pulse shaper (Fig. 1) contains a D-flip-flop 1, the inverse output of which is connected to the output bus and through delay element 2, consisting of an even number of a sequence of connected inverters 2-1 ... 2-n, with its R- input, and the second input element And 3, the output of which is connected to the C input of the D-flip-flop 1, the second input of the element And 3 is connected to the control bus 4 and to the R input of an additional

0 flip-flop 6, the d-input of which is connected to the bus 5 controlling the operating mode, the C-input with the output bus, and the inverse output with the D-input of the D-flip-flop 1.

The pulse shaper can operate in two modes: one-shot mode and one-shot mode. Moreover, the duration of the generated pulses is determined by an even number of inverters 2-1 ... 2-p delay element 2. Operation mode

0 shaper is caused by the supply of a corresponding potential — logical o or logical 1 — to the D input of the additional D flip-flop 6.

In the initial state, on the control bus 4, there is a potential of logical O (Fig. 2a) and, as a result, D-triggers 1 and B are in the zero state (Fig. 2c, d, e).

In the one-shot mode, the shaper operates as follows.

From the bus 5 of the operating mode control, the d-input of the trigger 6 is given a logical 1 signal (Fig. 26) and when a voltage drop of the control 4 of the voltage drop 0/1 is removed, the prohibition from the D-trigger b is removed, the And 3 element triggers and D-flip-flop 1. After time T, determined by the signal passing time through delay element 2, a logic O signal appears at the output of this element, which, affecting the setup R input of D-flip-flop 1, returns it to zero condition. Thus, at the outputs of the O-trio-gera 1, one pulse is generated. The voltage drop 0/1 at the inverse output of D-flip-flop 1 translates an additional D-flip-flop 6 into one state. The logic signal O from its inverse output goes to the D-input of D-flip-flop 1, and with the appearance of a voltage drop 0 / 1 at the output of delay element 2 D-flip-flop 1 will confirm its zero state. In such a state, the device will remain until the voltage drop 1/0 arrives at the control bus 4, which returns the device to its initial state.

In the generator mode, the device operates as follows.

The D-input of the trigger 6 from the bus 5 controls the operating mode of the device is given a logical O signal. When a voltage difference 0/1 appears on the bus 4 of the control, the element 3 and the D-flip-flop 1 are triggered. After time T, the D-flip-flop 1 returns in the zero state and the voltage drop 0/1 from its inverse output through time T acts on its R and C inputs and, since the D input of the D flip-flop 1 constantly has a logical 1 signal, since D -trigger 6 is in the zero state, D-trigger 1 goes into one state again e.

Thus, at the outputs of D-flip-flop 1, a series of pulse sequences with a period of 2T will be formed.

When a logical O signal is applied to the control bus 4, the input stops. effecting signals on the C input of the D flip-flop 1, and if the last pulse of the series had not been fully formed by the time the control signal ended, i.e. D-flip-flop 1 will be still in the single state, the pulse shaping process will continue until the logical O signal from the 5 inverse output of the D-flip-flop 1 through the delay element 2 arrives at its R input. If the D-flip-flop 1 is in the zero state by the time the control signal ends, the pulse shaping process stops immediately. The effect of impulse noise with signal levels corresponding to a logical O and duration less than T is significantly weakened, since if D-flip-flop 1 is

5 being in the single state, the impulse noise on the bus 4 of the control device only confirms its state, and if the d-flip-flop 1 is in the zero state, then the impulse noise cannot

0 to affect its C-input, since the element FROM at this time will be prohibited by the second input.

Thus, the introduction of an additional D-trigger. the element of and and new communications

five . allows you to extend the functionality: the formation of both a single pulse and a sequence of pulses of undistorted duration, which makes it possible to use it

0 in the devices of automation and computing.

Claims (1)

Invention Formulation pulse generator containing a D-flip-flop. inverse output of which 5 is connected to the output bus and through a delay element, consisting of an even number of series-connected inverters, is connected to its R input, characterized in that. that in order to expand the area 0, by forming both a single pulse and a sequence of pulses of undistorted duration, a control bus, an operating mode control bus, an additional D-flip-flop and an And element, whose output is connected to the C-input of the D-flip-flop, the first input from the output of the delay element, the second input is with the control bus and with the R-input of the additional D-flip-flop, the D-input of which is connected to the operating mode control bus, the C-input with the output bus, and the inverse output with the D-input D- trigger FIG. 2