SU1432757A1 - Device for monitoring repetition sequence of pulsed signals - Google Patents

Abstract

The invention can be used in automation and computing devices for controlling pulse sequences. The purpose of the invention is to increase the reliability of the control and expand the functionality

Description

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The 11th possibilities by defining the nature of the failure - is achieved by introducing the AND / AND-NOT 4 element, timed triggers 3, .n, short-circuits 7.1-7.P-1 of the second group, RS-triggers 9..n-1 of the third group , And 6.1-6.P-1 elements with a different number of inputs, an OR element 0. 0. The device contains two-port elements AND 1.- 1.p, RS-triggers 2.1-2.P of the first group, input terminals 5.1-5 .P, pulse shaper, 8, first element AND II, second element AND 12, tina Continue monitoring 13, RS-trigger 14, bus Fail 15, multi-input element OR

16, The introduction of these elements and their connections allow the formation of a Failure signal, both when the order of signals arriving at the input signal and when the signal at the input signal is constant, when there is no signal at the input bus, when there are several signals instead of one irrespective of the temporal position of the excess signal, as well as expanding the functionality, since If you analyze when the outputs of clocked triggers, RS-triggers of the first and third groups fail, you can determine the nature of the failure. 1 silt

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The invention relates to a pulse technique and can be used in automation and computing devices for controlling pulse sequences.

The purpose of the invention is to increase the reliability of control and expand functionality by determining the nature of the failure.

The goal is achieved by introducing into the device an AND / AND-NOT element, clocked triggers, (n-1) RS-triggers of the second and third groups, (n-1) element AND with a different number of inputs and an OR element, which allows to increase the reliability control of the sequence of alternating pulse signals, since the device generates a signal both when the order of the signal on the input bus is violated and when the signal on the input bus is constant, when there is no signal on the input bus, when several signals are received instead of one tive of excess time position signal and expanded functionality, as analyzed by fault condition outputs clocked flip-flops, RS-flip-flops of the first and third groups can be determined character SBO

The drawing shows a functional diagram of the device for controlling the sequence of alternating pulsed signals.

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The device contains p two-input elements And 1.1-1, p, p RS-flip-flops 2.1-2.P of the first group, p clocked triggers 3.1-3, p, element I / I-HE 4, p input bus 5.1-5.P, (p-1) elements And 6.1-6.1P-1, with a different number of inputs, (p-1) RS-flip-flops 7.1-7. second group, pulse shaper 8, (p-1) RS-flip-flops 9.1-9.p-1 of the third group, element OR 10, first element 11, second element 12, bus 13 Continue monitoring, RS-trigger 14, bus 15 Failure, multi-input element OR 16.

The device includes p-two-input elements AND ll-ln, the outputs of which are connected to the S-inputs of the corresponding 1x RS-flip-flops 2.1-1.n the first group, the first inputs with the outputs of the corresponding-clogging triggers 3.1 - Z.p and the corresponding inputs of the AND / AND-NOT 4 element, - and the second inputs - with the corresponding input buses 5.1t5.p, with the clock inputs of the corresponding clocked triggers 3.1- Z.p, with the first inputs of the corresponding shdh elements And 6.1-6. N- with a different number of inputs, and starting from the second input of the second two-input element And 1.2 are connected to the S-input We give the appropriate RS-flip-flops 7.1-7.p-1 of the second group, S-input of the (n-1) -th RS-flip-flop 7, n-the second group is connected to the input of the driver of the 8th pulse, R-inputs of the RS-flip-flops 7.

7. P-1 of the second group are connected to R-BX dami clock; x triggers 3.1-Z.p, RS-trigger OB 2.1-2.P of the first group, RS-flip-flops 9.1-9, p-1 of the third group, with the output of the element OR 10, and the ip-outputs of the trigger 7.1-7.P-1 with the inputs of the elements AND 6.1-6.P-1 with a different number of inputs, and the inverse outputs of the RS-6 are connected to the inputs of the K-go of the element I 6 the 7K-7.P-1 flip-flops of the second group from the K-th to (n -) - outputs of the elements 6.1-6, 6, n-1 with different number of inputs are connected to the S-inputs of the corresponding RS-flip-flops 9.1-9. P-1 of the third group, the outputs of which are connected to the corresponding The inputs to the inputs of an AND / AND-NOT 4 element, the inverse output of which is connected to the first input of the first element I 1 1, and a direct output to the first input of the second element 12, the second input of which is connected to the output of the pulse former 8 and to the second input of the first element AND 1I, and the output is with the first input of the element OR 10, the second input of which is connected to the input pin 13. Continue monitoring with the R-BXO or RS flip-flop 14, the output of which is connected to another 15 Fault, and the R input to the output of the multi-input element OR 16, n inputs of which are connected to the outputs of the corresponding RS-flip-flop in 2.1-2, p of the first group, and (n + 1) -th input - with the output of the first element And 11.

The device works as follows.

All the memory devices are reset to the initial state by a signal from the bus 13 Continue monitoring, at the same time at the outputs of clocked triggers 3.1-Z.p, RS-triggers 2.1-2.P. Of the first group, RS-triggers 9.1-9.P-1 and the third group and the RS-flip-flop 14 - zero signals, on the inverse outputs of the RS-flip-flops 7.1-7.P-1 of the second group - single signals.

Consider the operation of the device with the correct alternation of input pulsed signals. The pulse signal from the first bus 5.1 goes to the first input of the first clocked trigger 3.1 and through the element 6.1 - to the S input of the first RS-schemer 9.1 of the third group, and sets the leading edge at the output of the RS-flip-flop 9.1 and the falling edge at the output of the first

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Clocked Trigger 3.1 single signals.

The output of the first two-input element And 1.1, and, therefore, the S-input of the first RS-flip-flop 2.1 of the first group does not pass a pulse signal from the first input bus 5.1, because resolving a single signal at the second input of the first two-input element And 1.1 appears the output of the first clocked trigger 3.1 only on the trailing edge of the pulse signal from the first bus 5.1.

With the correct sequential alternation of signals on the input buses 5.2-5. P, the pulse signal from the corresponding bus 5.2-5. P is fed to the first input of the corresponding element AND 1.2-ln, to the clock input of the co-ordinated OTBeTCTByioDiero 3.2-W. to the S-input of the corresponding RS-flip-flop 7.1-7.P-1 of the second group and through the corresponding element AND 6.2-6.P-1 to the S-input of the corresponding RS-flip-flop 9.2-9.P-1 of the third group On the inverse the output of the corresponding RS-flip-flop 7.1-7.P-1 of the second group and at the output of the corresponding RS-flip-flop 9.1-9.P-.1 of the third group of mouth Zero and single signals are generated respectively, and a single signal is set on the falling edge of the pulse signal at the output of the corresponding clocked trigger 3.2-H. p.

Zero signals on the inverted outputs of RS-flip-flops 7.1-7.P-1 with the correct alternation of pulse signals on the input buses 5.2-5.P do not affect the further operation of the device,

At the output of the corresponding two-input element I 1.2-ln and, therefore, to the S input of the corresponding RS flip-flops 2.2-2.P of the first group, the pulse signal from the corresponding input bus 5.2-5.P does not pass, because the enabling single signal on the second the input of the corresponding two-input element AND 1.2-ln appears from the output of the corresponding clocked trigger 3.2-З.п only on the rear edge of the pulse signal from the corresponding input bus 5.2-5.p.

As a result, after all the pulse signals were correctly received, the output of all clocked 3.1-Z.p. triggers, all RS-triggers, 9.1-9.p-1

of the third group and, therefore, at all inputs and direct output of the AND / AND-NO 4 element there will be single signals, and at the output of all RS-flip-flops 2.1-2, n of the first group, at the inverse output of the AND / AND-NE element and the output of the multi-input element OR 16 will be zero signals. Therefore, at the output of the RS flip-flop 14 and the output bus 15, the signal will not fail, and the pulse signal generated at the output of the pulse shaper 8 with a delay relative to the trailing edge of the pulse signal will pass through the elements AND 12 and OR IO to R- the trigger inputs and reset the device.

When it arrives at any of the input busbars 5.1-5, p two pulsed signals instead of one, the device generates on the output bus 15 Failure an interrupt signal in the order of alternation as follows.

The pulse signal, which appeared again on the input bus 5.1-5.P, is fed to the first input of the corresponding two-input element AND 1.1-1.1, the second input of which already contains an allowable single signal from the output of the corresponding clocked trigger 3.1-3.p. Therefore, the second signal from the input bus 5.1-5.p will pass to the output of the corresponding two-input element I.1.1-1.P and the S input of the corresponding RS flip-flop 2.1-2.P will go in and set its c output signal at its output which through the corresponding input of the multi-input element OR 16 goes to the S-input of the RS-flip-flop 14. As a result, the output of the RS-flip-flop 1A and the output bus 15 will generate a signal

In the absence of a pulsed signal, the presence of a constant signal on one of the input buses 5.1-5.p-1 at the output of the corresponding clocked trigger 3.1-Z.P-1 a single signal will not be generated. As a result, on the forward and inverse outputs of the AND / AND-HE 4 element there will be zero and single signals, respectively. Therefore, the pulse signal generated at the output of the pulse driver 8, with a delay relative to the trailing edge of the nth signal and the pulse signal, through the AND 11 element and the multi-input element OR 16 goes to the S-input of the RS flip-flop 14. At the output of the RS flip-flop 14 and the output igine 15 will be a failure signal. In the absence of an n-th pulse signal or its constant level, the output of the n-th clocked trigger Z.p does not produce a single signal, and a pulse signal will not be generated at the output of the pulse shaper 8, which ensures the formation of an Failure signal on the output gain 15. After the arrival of the first pulse signal from the input bus 5. I on the output bus 15 will form a signal Fault as if the incoming pulsed pulse signal.

When a pulse signal arrives at the higher input bus, before the pulse signals from the input bus with a smaller number, i.e. in case of violation

the order of alternation and ffly of signals, the formation of a signal Fault on the output bus 15 occurs as follows. The pulse signal that came through the input control earlier pulse signals on the input bus with

a lower number, sets the leading edge on the inverse output of the corresponding RS-flip-flop 7.1-7.P-1 of the second group, the zero signal,

which prohibits the receipt of pulse signals from the input bus with a lower number through the corresponding elements And 6.1-6.P-1 to the 8-inputs of the corresponding RS-flip-flops 9.1-9.P-1

the third group, the outputs of which even after the arrival of all pulsed signals will be zero signals. As a result, on the direct and inverse outputs of the AND / AND-NO 4 element will be

zero and single signals, respectively. Therefore, the pulse signal generated at the output of the pulse driver 8 with a delay relative to the trailing edge of the nth pulse signal will go through the S-input of the RS-flip-flop 14 through the element I G1 and the multi-input element OR 16. At the RS-flip-flop 14 and output 15 a failure signal will be generated,

In the absence of an n-th pulse signal or its constant level, the output of the n-th clocked trigger Z.p does not produce a single signal, but at the output of the 8th pulse generator it does not

a pulse signal J will be generated which ensures the formation of a Failure signal on the input bus. However, after the first pulse signal arrives from the input 5.1 bus, the output:

Bus 1 5 will be formed by cnrncUi Fault as if an extra signal was received.

By monitoring the outputs of clocked 3.1-Z.p and RS-flip-flops 2.1-2, p, 9.1-9.P-1 of the first and third groups, respectively, you can accurately determine the nature of the failure.

Thus, the proposed device generates a fault signal in case of any disturbance in the sequence of alternating pulse signals, which increases the reliability of the control and also allows determining the nature of the fault.

Claims (1)

Formula from. bratis A device for controlling the sequence of alternating pulse signals, containing n input buses, a multiple input element OR, an RS trigger, whose R input is connected to the bus Continue monitoring and output to the bus Fault, first and second elements AND, pulse shaper, output which is connected to the first input of the first element I, n of the two input elements I, the first inputs of which are connected to the corresponding input buses n, the RS-flip-flops of the first group, the S inputs of which are connected to the outputs of the corresponding two input elements I, i.e. that, in order to increase the reliability of monitoring and expanding the functionality by determining the nature of a failure, an AND / AND-NOT element, p-triggered triggers are added to it, the clock inputs of which are connected to the corresponding input buses, n-1 RS-triggers second groups, n-1 elements And with a different number of inputs, n-1 RS-trigger3273 8 of the third i-pynribs and zleme; r: SUBi, the left input of which is connected to the R-BXO- house of the RS flip-flop, and the second input - to the output of the second element And, the first input of which is connected to the output of the pulse shaper, and the second input - to the direct output of the element AND / AND-NOT, the inverse output of which is connected to 0 by the second input of the first element AND, the output of which is connected to the first input of the multi-input element OR, the output of which is connected to the S input of the RS trigger and the remaining inputs to the outputs of the corresponding RS trigger of the first group whose R inputs are connected to the output of the element OR, with R-inputs of RS-flip-flops of the second and third groups and with R-inputs of tact 5ye rx 0 triggers, the outputs of which are connected to the second inputs of the corresponding two-input elements AND, and with the corresponding inputs of the element AND / AND-NOT, the clock inputs of the timed triggers 25 from the first to (p-1) -th are connected to the first inputs of the corresponding elements AND with a different number of inputs, and the clock inputs of clocked triggers from the second to the nth with S-inputs of co30 corresponding RS-flip-flops of the second group, S-input ( p-1) of the second group RS-flip-flop is connected to the input of the pulse former, the inverse outputs of the RS-flip-flops of the second group are connected to the inputs of the AND elements with different numbers of inputs, and they are connected to the inputs of the K-th of these elements. here are the inverse outputs of the RS-flip-flops of the second group from K-th to (p-1) -and, output 40 elements And with a different number of inputs are connected to the S-inputs of the corresponding RS-flip-flops of the third group, the outputs of which are connected to the corresponding remaining inputs of the element 45 AND / AND-NO.