SU1497741A2 - Reversible counter control unit - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automatic control systems and in measuring systems using reversible counters, and is an improvement of the device according to the author. N1293837. The aim of the invention is to increase the reliability of the operation. To achieve the goal, the elements And 16,17, the trigger 18, the elements And 19,20, the elements OR 21,22 are entered into the device. The device also contains input buses 1,2, elements NOT 3.4, triggers 5-7, delay element 8, trigger 9, delay element 10, element OR 11, element 12 and output buses 13-15. The increase in the reliability of functioning is due to the correct functioning and in case of an unequal amount of mutually overlapping pulses in the input buses. 1 il.

Description

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The invention relates to a pulse technique and can be used in automatic control systems and measurement systems using reversible counters.

The purpose of the invention, an increase in the reliability of operation, is achieved by introducing new structural elements that ensure correct functioning and in the case of an unequal number of mutually overlapping time impulses on the input tires.

Figure 1 shows the block diagram of the described control device for the reversible counter; FIG. 2 shows timing diagrams explaining his work.

The device contains the first 1, the second 2 input buses, the second 3, the third 4 NOT elements, the first 5, the second 6 triggers, the trigger 7 and the delay element 8 that make up the first pulse shaper; trigger 9 and delay element 10 constituting the second pulse driver; element OR 11, first element NOT 12, first second and third output buses 13-15, first 16, second 17 elements AND, third trigger 18, third 19, fourth 20 elements AND, first 21, second 22 additional elements OR.

Input bus 1.2 connected to the clock inputs of the triggers 5.6, respectively, with the inputs of the installation of zero triggers 6.5, respectively, with the inputs of the elements NOT 3.4, respectively, and the first, second, respectively inputs of the element And 17 output bus 13 connected to the output element OR 11, the first and second inputs of which are connected respectively to the outputs of the first and second pulse formers; the output bus 14 is connected to the output of the element NO 12, the input of which is connected to the output bus 15 and to the output of the second pulse driver; the outputs of the NOT elements 3.4 are connected respectively to the clock inputs of the first and second pulse formers, the resolution inputs of which are connected respectively to the outputs of the elements OR 21,22, the first inputs of which are connected respectively to the outputs of the elements AND 20.19 the first inputs of which are connected with the outputs of the elements NOT 4.3, respectively, and with the first, second inputs of the element And 16, the output of which is connected to the input of the zero setting of the trigger 18, the clock input of which is connected to the output of the element And 17; the inverse output of the trigger 18 is connected to the information input of the trigger 18 and with the second inputs of the elements And 19,20; the direct outputs of the triggers 5.6 are connected, respectively, to the second inputs of the elements OR 21,22, the information inputs of the triggers 5.6 are connected to the unit potential (not shown).

The information inputs of the trigger 7 are connected to the resolution inputs of the first, second, respectively, pulse shapers, clock inputs of which are connected to clock inputs of the trigger 7.9, respectively, the forward outputs of which are connected to the outputs of the first, second, respectively, pulse shapers, n with inputs, elements 8, 10 delays respectively. The outputs of which are connected to the inputs of the installation to zero triggers 7.9, respectively.

Figure 2 shows the timing diagram of the signals on the same tires and the outputs of the same elements.

The control device reversible counter works as follows

In the initial state, the triggers 5 and 6.7 and 9 and the trigger 18 are reset (to simplify the reset circuit of the triggers not shown in Fig. 1). Element And 17 is closed with zero signals from the input bus 1.2, And element 16 is open with single signals from the outputs of the elements NOT 3.4. Elements And 19, 20 are opened with single signals with you} soda elements of NOT 3.4, respectively, and with the inverse output of trigger 18. On bus 1 3 - zero signal, on buses 14 and 15 - single and zero signals, respectively.

On the leading edge of the positive pulse arriving via bus 1, the trigger 5 switches to one state. On the falling edge of the same pulse, information from the output of trigger 5 is recorded in trigger 7. When set to one trigger 7, the signal from its output goes through the element OR 1I to the output bus 13 of the account, while maintaining the same direction of the account, i.e. a single signal on the output bus 14 and a zero - on the output bus 15. Through

the time interval for the signal sig nlla on the delay element 8 at the output of the latter appears a signal switching the trigger 7 to the initial zero state, and the formation of the signal on the counting bus 13 ends (see the diagram in figure 2),

With the arrival of a pulse on bus 2, on the leading edge of a pulse, trigger 6 is switched to one state and trigger 5, to zero,

On the falling edge of the same pulse, information from the output of the trigger 6 is recorded in the trigger 9. When the trigger 9 is set to one, the signal from its output goes through the OR 11 element to the counting bus 13. In this case, after the installation of the trigger 9, the account changes, ie A zero signal appears on bus IA, and a single signal appears on bus 15. At the same time the signal from the output of the trigger 9 is fed to the input of the element 10 delay. After a time delay of the signal on the delay element 10, the trigger 9 is switched to the initial zero state, and the formation of the signal on the counting bus 13 ends. Towards

0

five

zero signals, therefore, at the end of the input pulses on tires 1.2, the triggers 7.9 confirm their initial zero state. In addition, at the end of the input pulses, the element AND 16 opens, a single signal from the output of which switches the trigger 18 to the initial zero state. When entering the next 1.2 overlapping pair of pulses over the tires 1.2, the device operates in the same way.

Consider the operation of the device when entering through the input buses 1 and 2 unequal number of mutually overlapping pulses. For example, the diagram of FIG. 2 shows one pulse on bus 2, overlapping in time by two pulses on bus 1.

With the arrival of the first pulse through the slit I, the trigger 5 is triggered to one and 5, the zero state of the flip-flop 6 is confirmed, the elements of AND 19 are closed, OR 22. With the arrival of the pulse on the bus 2 then it switches to the zero state

0

The calculation of the counting takes the initial value 30 trigger 5, remains in the zero state (see the diagram in figure 2).

Upon receipt of the next pulses on buses 1 and 2, the device operates in the same way. At the same time, at the end of each of the input pulses, element 16 is turned off, a single signal from the output of which confirms the initial zero state of the trigger 18.

With the arrival of the tires 1, 2 overlapping in time of paired pulses, the device operates as follows.

On the leading edge of the pulse received on bus 1 (in the diagram of FIG. 2, the leading one), trigger 5 switches to one state. On the leading edge of pulse on bus 2, trigger 5 returns to its initial state, And 17, a single output signal which the trigger 18 switches to the single trigger state, the trigger 6 remains in the initial state. The zero signal from the inverse output of the trigger 18 closes And 19, 20 elements on the second inputs. On the outputs of the OR elements 21, 22 and respectively on the information inputs of the triggers 7.9

SRI trigger 6, the elements AND 20, OR 21 are closed, AND 17 is opened. On the leading edge of the pulse from the output of the element And 17 the trigger 18 switches to one state, while the zero signal from its inverse output goes to the second inputs of the elements AND 19 and 20.

Since the output of the element OR 21 is a zero signal, at the end of the first pulse on bus 1, trigger 7 confirms its zero state. The element closes AND 17.

With the arrival of the second pulse

along the bar I (see the diagram of Fig. 2), element 17 again opens, the output signal of which switches to the zero (initial) state trigger 18, and to the second inputs of the elements

Both 19 and 20 receive a single signal from the inverse output of the trigger 18. At the end of the pulse, bus 2 is successively opened with elements AND 20, OR 21, a single signal arrives at the information input of the trigger 7, therefore the trailing edge of the second pulse on bus 1 switches to one state trigger 7, at the output of which a pulse is generated, coming through the element OR 1 to the output bus 13 of the account. At the same time, the previous counting direction is preserved, i.e. a single signal on the output bus 14 and a zero signal on the bus 15. In addition, at the end of the second pulse on bus 1, AND 19, OR 22, AND 16 elements are opened (the output signal of which confirms the zero state of trigger 18), the device returns to its original state the

Thus, when an unequal number of pulses mutually overlapping in time arrives on the output buses 1 and 2, by the time the last (in time) input pulse ends, the trigger 18 will be in the zero state and the AND 19, OR 22 elements or the AND 20 elements will be opened, respectively. OR 21, as a result of which a pulse will be formed on the falling edge of this pulse on the output bus 13 of the count. In this case, the counting direction will correspond to the input bus, the input of which will receive one more pulse compared to the other input bus,

When entering the input buses and 2 of any equal number of pulses mutually overlapping in time, by the time the last (in time) input pulse terminates, trigger 18 will be in a single state, elements AND 19 and 20, OR 21 and 22 will be closed, therefore on the falling edge of this pulse, the triggers 7 and 9 confirm their zero state.

Thus, the design features of the proposed technical solution allow to expand the possibilities

device operation, to increase the reliability of its operation.

Claims (1)

Invention Formula The control unit of the reversive counter according to the autor. No. 1293837, characterized in that, in order to increase the reliability of the operation, the third trigger, the first, second, third and fourth elements of AND are entered into it, and the discharge between the forward output of the first trigger and the output output of the second pulse generator and the second output of the second trigger are entered into it. the trigger and the resolution input of the second pulse driver, the first and second additional elements OR, respectively, are entered, the first inputs of which are connected respectively to the outputs of the fourth and third elements AND, the first inputs of which are connected respectively, with the outputs of the third and second elements are NOT and are connected respectively to the first and second inputs of the first element I, the output of which is connected to the input of the zero setting of the third trigger, the clock input of which is connected to the output of the second element And, the first and second inputs of which are connected respectively to the first and the second input bus, the inverse output of the third trigger is connected to the information input of the third trigger and the second inputs of the third and fourth elements AND, the direct outputs of the first and second triggers are connected Nena respectively to second inputs of the first and second additional elements or their outputs connected respectively to the inputs of the first resolution and second pulse shaping. Editor A.Makovska Compiled by Ranov Tehred A. Kravchuk Order 4456/55 Circulation 884 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, 4/5 Raushsk nab. "Tog er 3 :: u :: 5 fx С 3 ::, Corrector I.Gorn Subscription