SU1226629A1 - Device for converting pulse train - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automatic monitoring and control systems, as well as in information collection and processing systems. The purpose of the invention is to improve noise immunity and expand the scope of application due to the operation of the device with a series, the pulses in which have any duration and frequency within a given frequency range. Expansion of functionality is provided by determining the even or odd number of pulses there is in the received series. The device contains logical elements (LE) OR 3 and 4, 11 and 12, LE I-NOT 17 and 18, LE And 1, inverter 2, triggers 5 and 6, tires - output 7 and 20, 21 and 22, input 19, pulse expanders 8, 9 and 10, shapers 13 and 14, 15 and 16 pulses. The reliability of the device is enhanced by eliminating its false positives as a result of an increase in noise immunity. 1 il. I (L

Description

The invention relates to a pulse technique and can be used in automatic control and monitoring systems J in systems for the collection and processing of information.

The purpose of the invention is to increase the noise tolerance and expand the scope of application by ensuring the possibility of the operation of the device from the series No. 5 pulses in which the duration and any frequency within a certain frequency range and are wide. functional possibilities by providing an even or an odd number of pulses in the incoming series.

Pa the drawing shows a glitri-, cell block diagram of the device ..

The device contains an element And 1

inverter 2; the first and second elements of EE OR 3 and 4; the first and second triggers 5 and 6e of the first of which are connected by the first input to the first input of the OR element. The forward output and the first input of the second trigger are connected respectively to the first output bus 7 the device and the output element AND 1, the first, second and third expanders 8 - 10 pulses, the third and fourth elements OR 11 and 12, the first, the second S third, fourth shapers .13 - 16 ims and nepBbtti and the second elements 17 and 18 ;, the input of the first imager 13 pulses is connected to an outwardly sheer 19 device5 output connected

 With the counting input of the first trigger to

 from the first input is a second element; an OR 4 5 the second input of which is connected to the output of the first trigger-5.,

 and the output of the second ISH 4 - Tapes element connected in series the first expander of 8 pulses, the second generator of 14 pulses and the inverter 2 is connected to the first input of the “first element IS-NOT 17 output of the first raster-8 cursor of the pulses connected to the second input of the second element I-NOT 18 "whose output through the third forcher 15 pulses is connected to the first VOG4U input Reset the first trigger 5 and to the second input of the first element I - NOT 17 5 whose output is connected to the second input of the second trt-ygger, kn the output of which is connected to the second input The first element of UTI 3a and its outlet through the second expander 9 of the impuppers are connected to the second output bus 20 of the device and to the first input of the element I 1, the output of which is connected to the third output bus of the device 21, the second input of the element And 1 is connected to the fourth input bus 22 of the device and to the output of the third element OR 11, the first input of which is connected to the second input of the second element OR 4 and to the first input of the second element NAND 18; and the second input of the third element of the IGO 1 11 is connected through the fourth fourth shaper of 16 pulses and the third expander of 10 pulses connected to the output of the fourth element OR 12, the first and second inputs of which are connected respectively to the counting input and the inverse output of the first trigger.

The device works as follows

The first impulse as well as all the odd pulses from a device of the pulse train arriving at the input bus 19 pass through the shaper 13 pulses; the element OR 4, the heater 8 pulses, the shaper 14 pulses, the inverter 2; AND-NOT element 17; causing a pulse with a duration of q at the output of the output, which throws trigger 6 and triggers the appearance of a pulse at its code, the last front of which lags behind the leading front of the first input:: - I1 4 1 pulse by the value i. On the left- and: e of this pulse indicates the rocking of a series of pulses at the input pulse: e 19 of the device. At the exit Ele. I., AND-NO 18; but. consequently, the output of the impulse generator 15 pulsioii sn; there are no gnals, since from the moment of the preceding preceding - ;, ttsogo and before the start of the subsequent ig-shul L from the output, the expander has 8 pulses on the first one

The second pulse, as well as all the even ones from the series of pulses received on the input bus 19 of the device, pass r through the driver of .13 pulses, an element of the Scientific Research Institute 12, a dilator of 10 pulses | the driver of 16 pulses 3 caused at the output of the latter and shyl ,, whose leading edge lags behind the leading edge of the second or corresponding even pulse by the value of t. At the exit

element OR 11 signal is absent, because at the time of arrival of the signal from the output of the imager 16 pulses to the second input of the element OR 11, it is closed at the first input by a single potential from the direct output of trigger 5.

There is no signal at the output of the NANDI 18 signal, since from the moment the previous one ended and until the beginning of the subsequent pulse 7 from the expander 8 output, the AND 18 element is closed at the first input.

The last odd pulse from a series of pulses arriving at the input of the device leads to the appearance of a signal at the output of the NE-18 element, since at the end of the pulse G Cr of the output of the expander 8 pulses corresponding to the last pulse of the series, there is a single potential. At the output of the imaging unit 15 pulses, a signal with a duration t arises, which is delayed relative to the last pulse of the series by an amount i. This signal prohibits the passage of the pulse arriving at the first input of the element AND-HE 17 and its output, and the signal from the output of the driver 15 of the pulses to the second input of the element AND-NOT 17 must arrive before the signal from the output of the inverter 2 to the first input the same NAND element 17. If a signal delay is not required due to the total proper response time of the shaper 14 pulses and inverter 2, then it is necessary to put a delay element between them.

The signal from the output of the pulse driver 15 resets the trigger 5, sets a zero potential at its direct output, and also arrives at the first input of the OR element 3, at the second input of which there is a zero potential. Therefore, at the outputs of the element OR 3, the expanders of 9 pulses, the element I 1, an output pulse appears on the output buses 20 and 21 of the device, which corresponds to the last odd impulse of the series and lags behind the value of L. On the leading edge of the pulse from the output of the element I 1, trigger 6 is reset on its forward

five

0

5 0 5 o

0

0 5

, e is set to zero potential. Consequently, a rectangular pulse is formed on the output bus 7 of the device, the duration of which is equal to the duration of the input series of pulses delayed relative to the first pulse of the series by the value t.

The last even pulse from a series of pulses arriving at the device leads to the appearance of a signal at the output of the element OR 11, since at the time of the arrival of the pulse from the output of the generator of 16 pulses to the second input of the element OR 11, at its first input there is zero potential from the direct output trigger 5. At the output of the element I 1, on the output buses 21 and 22 of the device, pulses appear that correspond to the last even pulse and are delayed relative to it by the value of t. On the leading edge of the pulse from the output of the element I 1, the flip-flop 6 is reset, and a zero potential is established at its forward odes. Consequently, a rectangular pulse is formed on the output bus 7 of the device, the duration of which is equal to the length of the input pulse train delayed relative to the first pulse of the LSA series by the value of i.

Since the trigger 5 is set to the same initial state by the Reset signal and the trailing edge of any even pulse, then with an even number of pulses in the input series, it is not necessary to give a Reset signal to the trigger 5. In addition, if during the implementation of the proposed device a trigger is not found, which is shifted from O to 1 to the initial state, then resetting the trigger 5 can be done by giving an additional impulse to its counting input.

As such an additional pulse, you can use a pulse from the output of the pulse driver 15, which is fed not to the bus bus, but to the first input of an additional element I, the output of which is connected to the counting input of the trigger 5, and the second input of an additional element I connected to the output of the driver of 13 pulses and

first. inputs of elements OR 4 and. 12.

When a single impulse or noise pulse arrives at the device input bus 19, then there is no signal at the device output bus 7 because simultaneously with the arrival of pulse 1 at the first input of the element IS-NOT 17, its first input is closed by an impulse, therefore at the output element AND NOT signal 17 is missing. The pulse from the output of the pulse driver 15 resets the trigger 5, returning it to its original state, and also arrives at the first input of the OR element 3, the second input of which has a inhibitory (single) potential, therefore, at the outputs of the OR element 3, the pulse extender 9 And 1, the output buses 20 and 21 of the device signals are missing.

Thus, the device for converting a series of pulses to single pulses does not respond. On the output bus 7 of the device, a rectangular pulse is formed, the duration of which is equal to the duration of the input pulse train delayed by an amount relative to the first pulse of the train. The last odd pulse of the series appears on the output bus 20 of the device, the last even pulse of the series appears on the output bus 22 of the device, and the last pulse of the series on the output bus 21.

The proposed device allows to increase the noise immunity, to expand the field of application of the device by allowing it to work with a series of pulses having any duration and any frequency within a certain frequency range, thereby eliminating the false alarms of the device, as well as expanding the functional possibilities by providing an even or odd number of pulses in the incoming series.

Claims (1)

Invention Formula A device for converting a series of pulses containing an element AND, an inverter, the first and second elements OR, the first and second uiii of the generator, the first of which is connected with the first input to the first input of the first element OR, the direct output and the first input of the second trigger are connected respectively to the first the output bus of the device and the output of the AND element, characterized in that that, in order to increase noise immunity, to expand the field of application by ensuring the operation of the device with a series, the pulses in which have any duration and any frequency within a certain frequency range, and extending its functionality by providing an even or odd number of pulses in the received series, the first, second and third pulse spreaders, the third and fourth element OR, the first, second, third, fourth pulse formers and the first and second elements of AND –NE, the input of the first pulse shaper are added to it and the output is connected to the counting input of the first trigger and with the first input of the second element OR, the second input of which is connected to the direct output of the first trigger, and the output of the second element OR through connected in series the first expander) pulses, the second pulse shaper and the inverter is connected to the first input of the first NAND element, the output of the first pulse expander connected to the second input of the second element And-HEj whose output through the third pulse shaper is connected to the first input of the first trigger and to the second input of the first element NAND, the output of which is connected to the second input of the second trigger, the inverse output of which is connected to the second input of the first OR element, the output of which through the second pulse expander is connected to the second output bus device and the first input element And, the output of which is connected to the third output bus device, the second input element And is connected to the fourth output bus device and to the output of the third element OR, the first input of which is connected to the second turn of the second 712266298 the OR element and to the first input, the second pulse spreader is connected to the N-th exhaust element, and the second, the fourth element input, OR, lane: The third element OR through the serial and second inputs of which the fourth connected forcibly is connected to the counting pulse counter and the third race and the inverse output of the first trigger, respectively.