SU822341A1 - Selector of intervals between pulses - Google Patents

Description

I

. The invention relates to a pulse technique and can be used in devices for extracting pulses having a specific repetition rate or duration.

A pulse selector, an impulse shaper elements I., an element OR, a trigger, a switch of selectable thresholds, a counter, a gate, a differential circuit and a diode are known.

The disadvantage of this selector lies in its low noise immunity. . . -. -.

The closest to the proposed is the selector of intervals between the signals containing the formers on the front and decay of the input pulses, the OR element, the trigger, the controlled generator, the counter, the waiting multivibrator, the formaker on the decay of the waiting multi vibrator and the AND pQ element.

However, this device is also not protected against short-term impulses of noise at the input, the effect of which during the formation of the enabling gate may result in a false output pulse.

The disadvantage of this selector is that a single interference pulse (after a prolonged absence of input signals), which arrived at the input of the selector during the enabling gate generated by the selector automatically with a predetermined time interval, can also cause a false output pulse. In addition, two interfering pulses with an interval of less than ––, specified, cause a false output pulse to be produced if the first pulse arrives at the collector input when the prohibition gate is formed, and the second - during the formation of the enable gate .

The purpose of the invention is to improve noise immunity.

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The goal is achieved. We mean that the pulse selector containing the front and rear edges driver, the information inputs of which are connected to the input bus, the AND-NOT output element, the first input of which is connected to the first output of the front edge driver, is connected to the second input the output of the K-trigger, D and C

0 inputs of which are connected to the outputs

a non-OR element, one input of which is connected to the initial installation bus, a counter, the first input of which is connected to the clock signal bus, and the outputs are connected to the inputs of the NAND element, the output of which is connected to the R input of the ZK flip-flop, are entered two: 1K -trigger, and the NAND element, the output of which is connected to the second input of the NOT-OR element, the third input of which is connected to the second output of the front-edge former, the second input of which is connected to the first output of the second jK flip-flop, the second input of which is connected to the second input of the rear driver its front, the R-input of the second ZK-flip-flop is connected to the initial installation bus, the K-input is connected to one output of the trailing edge former, the C-input is connected to the clock signal bus, and the R input is connected to the first output of the leading edge former, and the second the output of the rear-edge driver is connected to the R-input of the third ZK-flip-flop, D and C-inputs of which are connected to the output of the NOT-OR element, and the output of the third Zk-flip-flop is connected to the R-input of the counter, while the third inputs of the front-side shapers are connected to the bus clock signal

FIG. 1 shows a functional diagram of the proposed selector, FIG. 2 - time diagrams of his work.

The selector contains the front-edge driver 1, the rear phase-side driver 2, triggers 3-5, AND-HE elements 6-8, NOT-OR 9 element and counter 10. The input signal goes to bus 11, clock pulses to bus 12, start signals installation - on the bus 13. The device also contains a bus 14 output pulses. Shaper 1 front of the front consists of a trigger 15, and the driver 2 of the rear front of the trigger 16 and the inverter 17.

The device works as follows.

In the initial state on bus 13, the zero signal sets trigger 3 to the zero state, output 18 is a zero signal, followed by a 3-input trigger 16. Since bus 11 has a zero signal, then the output of the inverter 17 is a single signal enabling the switching of the trigger 16. On the decline of the first arriving clock pulse, the trigger 16 switches to the zero state — at the output 19 — a zero signal, and at the inverse output 20 a single signal. A zero signal at the R input of the trigger 15 forcibly sets it to the zero state, and at output 21, zero, prohibiting the operation of the AND-HE element 8,

at the output of the selector - a single signal. A single signal at output 20 permits switching of trigger 4. Since the input signal 22 of the element is NOT-OR 9 is zero, then at its output 23 is a single signal. At the end of the zero signal on bus 13, i.e. at the termination of a single signal at the output 23, the triggers 4 and 5 are set to the single state, on the inverse outputs 24 and 25 -. zero signals. The zero signal at the output 24 zeroes the triggers included in the counter 10 and prohibits its operation, and the zero signal at the output 25 prohibits the operation of the AND-HE element 8, the Selector is ready for operation.

The single signal on bus 11 disables the switching of trigger 15. Since there is a single signal at D-input of trigger 15, the trigger 15 switches to single and the next clock pulse returns to the zero state and trigger 3 after the decrease in the next clock pulse. switches to one state. A single signal at the output 21, formed as a result of the Tave switching of the trigger 15, does not pass to the output bus 14, since the second input of the AND-NE element 8 is zero, and the zero signal at the inverse output 26 of the trigger 15 forms a single signal at the output 23 of the element NON-OR 9, the decay of which confirms the unit state of the flip-flops 4 and 5. Due to the fact that the flip-flop 3 switches to the unit state, its inverted output 27 has a zero signal, and the zero state of the trigger clock is confirmed by the zero state of the trigger 15 .

The trigger 16 is forced to the zero state by a zero signal at its R input. By the decay of the next clock pulses, trigger 3 does not switch, since its D and K inputs have zero signals, and it retains its one state.

The decay of a single signal on bus 11 (i.e. after the end of the first input pulse) makes a count of the time interval between the input pulses as follows: a single signal appears at the output of the inverter 17, and since the output 18 of the trigger 3 is a single signal, then the trigger 16 is switched to one state by the decay of the first arriving clock pulse, the zero signal at the inverse output 20 switches the trigger 4 to the zero state, and the output 19 gives a single signal allowing switching to the zero state rigger 3.

Claims (2)

By the decay of the second arriving clock pulse, switching to the zero state (in the counting mode) of the trigger 16 and the trigger occurs. The last clock pulses confirm the zero state of the trigger 16, since its 3 input has a zero signal. Due to the fact that the trigger 4 switches to the zero state at its inverse output 24, a single signal enables the counter 10. After counting a predetermined time interval, a zero signal appears at the output 28 of the AND-NO element, switching the trigger 5 to the zero state, at the inverse output 25 there is a single signal permitting the operation of the NANDE element 8. After a time determined by instability on the arrival of input pulses with a set time interval, at the output 29 of the NESH element 6 a positive signal appears, which element is NOT - OR 9 switches triggers 4 and 5 to a single state, returning the selector to its initial state. Thus, in the case when the post-aggregation (after the first) input pulse does not arrive within a given time interval, the pulse generated at the output -29 of the AND-NE element 6 ensures that the triggers 4 and 5 return to the Initial state. When a single signal arrives on the selector bus 11 in the interval when the output 25 is a single signal (the time interval is equal to the specified one), the following happens: at the fade of the first incoming clock pulse, the trigger 15 switches to the single state, and after the second received clock pulse the pulse returns to the zero state (in the counting mode), and the trigger 3 switches to the single state. The single signal generated at the output 21 of the flip-flop 15 permits the output signal to be output, and a zero signal appears on the front of the second incoming clock pulse on the bus 14. From the time diagrams (FIG. 2) it can be seen that the minimum time interval at which a pulse can be issued on the G4 bus relative to the pulse on the bus 11, p. veins of time from the fall of the clock pulse to the front of the next clock pulse. At the same time, if the duration of the input pulse is short (less than the time from the fall to the front of the next clock pulse), then at the end of this short single pulse the zero input signal returns the trigger 15 to the zero state forcibly, i.e. short-term interference, the duration of which is less than the interval from the fall to the front of the clock pulse, cannot result in a false output pulse, due to the fact that the operation of the triggers 3, 15 and 16 and the IS-NE element 8 is synchronized with the clock pulses, and the trigger 3 controls the operation trigger in 15 and 16, consistently allowing the reception of single and zero information on the input selector. Thus, in contrast to the known selector, the proposed one does not produce a false output signal when exposed to a short-term noise input. In the selector, at the end of a predetermined time interval, a signal is generated at output 29, which, through the element NON-OR 9, triggers triggers. 4 and 5 to the initial state, therefore, the next single impulse of interference received on the bus 11 after a long absence of input pulses does not cause a false output signal, which also indicates a greater noise immunity of this selector compared to the known one. Due to the fact that from the inverted output 26 of the driver 1 signgs through the NOT-OR element 9 performs the initial installation of the triggers 4 and 5 and the selector as a whole into the initial state on the front of each single input signal, the output of the false output signal is excluded. the impact on the input of the selector noise interference pulses with an interval between them is smaller than the specified, which takes place in the well-known selector, which does not respond to input signals acting between the enabling gates. Claims The pulse spacing selector containing a front and rear edge driver, whose information inputs are connected to the input bus, an AND-NOT output element, the first input of which is connected to the first output of the front-edge driver, the second input is connected to the output of the ZK-trigger, 3 and C. inputs which are connected to the output of the element NOR, one input of which is connected to the bus of the initial installation, a counter, the first input of which is connected to the bus of the clock signal, and the outputs connected to the inputs of the element NAND, the output of which is connected to the R-input of the 3-flip-flop, characterized in that, in order to improve robustness, a 3-K flip-flop is entered into it, and an NAND element, the output of which is connected to the second inlet of the NOT-OR element, the third input is cheaply connected with the second output of the front-fronting device, the second input of which is connected to the first exit of the second E-K flip-flop, the second the input of which is connected to the second input of the trailing edge, j is the input of the second ZK flip-flop connected to the initial setup bus, the K input is connected to one output of the trailing edge imager, the C input is connected to the clock signal bus, a) the input is connected to the first output of the front-edge former; the second output of the rear-front former is connected to the R input of the third .ZK-trigger, tJ and C- whose inputs connected to the output of the element is NOT-OR, and the output of the third 3 K-trigger is connected to the R-input of the counter, while the third inputs of the front drivers are connected to the clock signal bus. Sources of information taken into account in the examination 1, USSR author's certificate No. 571893, cl. N.OZ K 5/18, 09.02.76. 2. USSR author's certificate f 613499, cl. H 03 K 5/20, 20,12.76. j; П П П П П П П П П П П П П 1 П Г | | P P f G | P P P P P P P P P P P 1, .11 Mil 11II 11