SU1177901A1 - Time discriminator of complete pulses - Google Patents

Description

The invention relates to a pulse technique and can be used in automation devices.

The purpose of the invention is to improve noise immunity by providing 5 the possibility of automatically forming the end of the selection interval at the end of the output selectable pulse coinciding with the strobe, which allows for 10 selection of whole information pulses of variable duration in a wide range of pulse durations and pauses regardless of the strobe duration, 5

Fig, 1 shows the functional-. Nal scheme of the proposed device; figure 2 - timing diagrams explaining his work.

The device contains. The first 1, 20

second 2 and third 3 triggers, element 4 delay, first 5 and second '

6 elements NAND, inverter 7, input bus 8, gate signal bus 9, output bus 10. 25

Triggers 1-3 can be performed on the elements AND-NOT 11-16.

The first input of the trigger 1 is connected to the bus 9 of the strobe signal, and its output is connected to the first input of the trigger ₃ θ

2. The second inputs of the triggers 1 and 2, the input of the element 4 delay and the first input of the element AND-NOT 5 are connected to the bus 8 of the input signal. The output element AND-NOT 5 is connected to the output bus 10, the first input of the trigger 3 and the first input element AND-NOT 6.

The second input of the trigger 3 is connected to the second input of the element AND-NOT 5 and

trigger output 2, second input

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element AND-NOT 6 is connected to the output of the trigger 3, and its output is connected to the third input of the element AND-NOT 5, the fourth input of which is connected to the output of the delay element 4.

To invert the output signal to the output bus 10 can be connected to the inverter 7.

The device works as follows. . 50

In the initial state, the buses 8 and 9 receive zero signal levels, while the outputs of the elements AND-NOT 12 and 5 are set to single signal levels, the output of trigger 55 2 is zero.

The zero level of the signal from the output of the trigger 2, is fed to the second input

trigger 3, the first input of which receives a single signal from the output of the element AND NOT 5.

The trigger 3 is set to a state in which the zero signal from its output goes to the second input of the element AND-NOT 6, the output of which is a single level.

When a single input signal (selectable or strobe) arrives at any of the inputs of the trigger 1, the output level of the corresponding AND-NE 11 or 12 element is set to zero. After the arrival of both input signals, trigger 1 remains in a state that occurs when the first of the input signals is acted upon.

If a selectable pulse arrives first, then the signal at the output of the element AND-NOT 12 remains single and after the arrival of the gate, the output signal of the element AND-HE.14 is set to a zero signal, which is fed to the second input of the element AND-NOT 5 and prohibits passage through it selectable pulse delayed by the element 4 delay.

If the strobe came first (FIG.

2 a) then the zero level of the signal of FIG. 26 is set at the output of the AND-NO element 12, this level remains even after the arrival of the selectable pulse (FIG. 289) The zero signal is set at the output of the IS-NOT 13 element (Fig.2g /. and the output of the element AND-HE 14 - single / Fig. 2 ^), which allows the input selectable pulse delayed by the delay element 4 (Fig, 2b) to pass through the element AND-HE 5 to the output bus 10 devices (figure 2.ZH).

This mode is not violated during the entire time of the gate and after its termination, since the trigger 2 "remembers" the action of the negative differential at the output of the AND-NOT element 12 and stores it until the completion of the selection cycle.

The inverted input pulse from the output of the element AND-NOT 5 also enters the first input of the trigger 3, which switches to the unit state £ 2 ^, in which, the single signal from the output of the element AND-NOT 15 enters the input of the element AND ~ NOT 6 and prepares it to trigger.

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1177901

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If the selectable signal ends before the strobe, then at its trailing edge, at the output of the NAND 5 element, a single signal level is generated, arriving at the first input 5 of the NAND element 6 prepared by the second input with a single signal from the trigger 3.

The zero signal from the output of the NAND 6 element (FIG. 2i.) Enters the third 10 input of the NAND 5 element and closes it, thereby restricting the selection interval immediately at the end of the selected pulse, preventing the impulse interference received on the bus 8 of the device after the end of the selected pulse.

After the strobe is terminated, at the output of element I-HE ^, a single signal is set, which arrives at the first input of trigger 2. When the monitored signal arriving on bus 8 takes a zero value, trigger 2 returns to its initial state, in which the zero signal with element AND-NOT 14 closes the second input element AND-NOT 5, and also enters the second ^L input trigger 30 3. Trigger 3 returns to its original state, in which

; signal of the zero level from the element: NAND 15 arrives at the second input of the element NAND 6, 35

A single signal from the element AND-NOT 6 prepares for the third input the element AND-NOT 5. passing through

it of the next selected pulse.

This completes the work cycle, for one strobe pulse a selection of one input pulse of arbitrary duration, both smaller and larger strobe,

Subsequent operation of the device is similar.

Only one impulse passes to the output bus 10 of the device. -NOT 6 immediately without additional delays, and thus the time interval for selection is limited regardless of the action of the gate pulse at this time, therefore the end of the selection interval in the proposed device is not specified by the duration strobe, and is set automatically at the end of a selectable pulse, the duration of which can vary widely, regardless of the duration of the strobe, the phase position of the selectable pulse can be unstable and change within the strobe, and the interference at the device input in the pause after the end of the selected pulse does not pass to the output through the element AND-NOT 5, closed on the third input by the zero signal from the element AND-NOT 6.

Ί.

'Figure 2

Claims (2)

TIME SELECTOR OF A WHOLE PULSES, containing the first trigger, the first input of which is connected to the gate signal bus, the second input - to the input signal bus, the second input of the second trigger, the input of the delay element and the first input The first element is NAND, and the output is to the first input of the second trigger, in contrast to the fact that, in order to improve noise immunity, a third trigger has been introduced, the first input of which is connected to the output of the first NAND element and the output bus, the second input is to the output of the second trigger and the second input of the first NAND element, and the second NAND element, the first input of which is connected to the output of the first NAND element, the second input to the output of the third trigger, and the output to the third input of the first AND element NOT, even- The rear input is connected to the output of the delay element. 1 zi „„ 1177901 one 1177901 2