SU978335A1 - Pulse duration selector - Google Patents

Description

(54) SELECTOR OF PULSES OF DURATION

The invention relates to a pulse technique and can be used in radio electronic devices, radar, radio navigation, computing and measuring equipment, in automatic control and regulation systems, discrete automation and telemechanics, as well as in television computing automatic systems. . A device of a similar purpose is known, which contains a matched delay line, the input and output of which are connected respectively to the first and second terminals of the AND element directly, and the drain through the HE ClJ element. The disadvantages of this device are the lack of limitation of the duration of selectable pulses from below, which leads to the complication of receiving devices in multichannel radar and radio navigation devices, where the limits of varying the durations of the pulses that must be distinguished on the receiving side are usually known; variable delay and change in the duration of the output pulse relative to the input and the dependence of these parameters on the duration of the input pulse. In addition, if the pause between adjacent pulses is shorter than the delay time, then at the output of this device pulses appear that are shorter than the duration of the selection range. Closest to the proposed is a selector that contains a delay line, the input of which is connected to the input bus, and the output to the first input of the And element, two triggers and the AND-NOT element, with the information inputs of the triggers connected to the input bus, the inputs syn: to the taps of the delay line, the direct output of the first trigger - to the reset input of the second trigger, the second input of the element AND and the first input of the element AND – НЁ, the inverse output of the second trigger - to the third input of the element And, and the direct output to the third, Rum inlet element AND-NOT, exit connected to the fourth input element And the reset input of the first trigger 2.

The main disadvantage of the known device is that the output can pass pulses whose duration is shorter than the duration of the selection range, and pulses whose duration corresponds to the duration of the selection range can disappear. This determines the low accuracy of selection.

The purpose of the invention is to improve the accuracy of pulse selection in a given range of durations while simultaneously ensuring a fixed delay of the output pulse relative to the input pulse and preserving the duration of the input pulse.

The goal is achieved by the fact that the first and second taps of the first delay line are connected to the clock inputs of the first and second triggers, respectively, to the device containing two triggers and the first delay line, the information inputs of which are connected to the input bus of the device. , the first input of which is connected to the output of the first trigger, and. an AND element, a clock pulse generator, a second delay line, a second NAND element, a differentiation circuit and a delay element, the input of which is connected through the differentiation circuit to the device input bus and information input of the second delay line, and connected to the first input of the And element, and the output connected to the reset input of the first delay line, the synchronization input of which is connected to the synchronization input of the second delay LINE and the output of the clock generator, and the outputs of the first delay line are connected to private inputs By resetting the second delay line, the common reset input of which is connected to the output of the element I, the second input of which is connected to the output of the second element AND-NOT, the first input of which is connected to the inverse output of the second trigger, the second input is connected to the output of the first trigger and the reset input of the second a trigger whose direct output is connected to the second input of the first NAND element, the output of which is connected to the third input of the second NAND element and to the reset input of the first trigger. The first and second delay lines can be executed in the form of shift registers containing n triggers, with the information input of each line

the delay is connected to the information input of the first trigger of the corresponding delay line, and the information inputs of the heading triggers are connected to you

by the moves of previous triggers, the synchronization input of each delay line is connected to the trigger synchronization inputs, and the reset input of the first delay line is connected to the reset inputs of the trigger network

delay lines, common reset input of the second delay line is connected to the first reset inputs of triggers of this delay line, the second reset inputs of which are connected to private reset inputs

Claims (2)

this delay line, the outputs of the first delay line are connected to the corresponding trigger outputs of this delay line, and the first and second branches of this delay line are the outputs of the hrt and (n − 1) th trigger, respectively. FIG. 1 shows a structural electrical pulse selector circuit for duration; FIG. 2 is a structural electrical delay line circuit. The pulse selector contains two triggers 1 and 2, two delay lines 3 and 4, two elements 5 and 6 INE, element 7 I, differentiation circuit 8, delay element 9 and generator 10 clock pulses. Each of the lines 3 and 4 of the delay is made in the form of shift registers containing n flip-flops 11 (11-1, 11-2 ,,,, 11-т,.,.,), Pulse selector in duration works as follows, In the original the position of the flip-flops 1 and 2 and lines 3 and 4 (i.e., flip-flops 11) are in the zero state, the element 6 is closed by a low potential from the trigger output 1. The input pulse goes to the information inputs of the lines 3 and 4 flip-flops 1 and 2 and to the input of the chain 8, In the delay lines the signal moves from the input to the output with a clock frequency of 10, If the input pulse has a long iii, ocTb is large is greater than the delay time on the first tap of line 3, then a logical unit and a trigger signal appears at the sync trigger input 1, 1 triggers to one state, opening element 6 on the second input. If the duration of this input pulse is less than the time the delay on the second branch of line 3, then the trigger 2 remains in the zero state, since at the time of arrival of the synchronization pulse from the second branch of line 3, the potential of logical zero is sent. The falling edge of the input pulse passes through circuit 8 and element 9. From the output of element 9, a short pulse with a logical logic potential enters the reset input of line 3 and sets it to its initial state. The rear edge of the input pulse does not pass to the common reset input of line 4 through element 7 since the second input of this element establishes a low potential from the output of element 6, therefore the input pulse remains in line 4 and arrives at the output of the pulse selector by duration, If the duration of the input pulse is less than the time delay on the first tap of line 1, the trigger 1 is set to the zero state, element 6 at the second input is closed by a low potential; from the output of trigger 1, a logical unit is set at the second input of element 7. On the falling edge of the input pulse passing through chain 8, and element 7, at the common input of the reset of line 4, appears with a short pulse of a logical unit, and the private inputs of the reset of this line from the outputs of line 3 receive signals of the logical unit corresponding to the recorded input pulse. Thus, in line 4, the inverse pulse of line 3 is recorded, i.e. the impulse that existed in line 4 is eliminated. Line 3, after the time determined by the delay time of element 9, is set to the zero state. If the input pulse duration is longer than the delay time on the second branch of line 3, then a logic unit signal appears at the synchronization inputs of triggers 1 and 2, and they switch to one state, and the output of element 5 sets a logical zero, which closes element 6 on the third input and returns the trigger 1 to the zero state; in turn, the logical zero signal from the output of trigger 1 is fed to the reset input of trigger 2 and sets it also to the zero state. At the output of element 5, a logical unit is established, which opens element 6 through the third input, at the output of element 6 a logical unit is established. The falling edge of the input pulse passes through circuit 8, element 7, which is open through the second input, to the common reset input of line 4, to the private reset inputs of which signals from the outputs of line 3 and through element 9 to the reset input of line 3 arrive. recorded in both lines 3 and 4, and then (on the falling edge of the input pulse) is erased, in this case the input pulse does not pass to the output of the device. To unify the element base, the delay element 9 can be made of several series-connected elements AND (OR -NOT). Carrying out the forced installation of triggers 11 of the delay line 3 to the zero state on the trailing edge of each input pulse eliminates the random coincidence of the signals of the forward and delayed pulses and the appearance at the device output of short impulse noise and suppression of useful pulses. Introduction to the device of the clock pulse generator, the second delayed-line line, the second NAND element, the differentiation circuit and the delay element, both delay lines made in the form of shift registers, made it possible to increase the pulse selection accuracy in a given range of durations, as in the second delay lines at any time always record only one of the input pulses. Therefore, any sequence of pulses does not lead to lolse triggers in the device, apart from the prototype, where a series of pulses, hit g, delay line, causes false alarms of the device. Claim 1. Pulse duration selector, containing two flip-flops and a first delay line, whose information inputs are connected to the device input bar, and the first and second taps of the first delay line are connected to the synchronization inputs of the corresponding first and second triggers, the first AND-NOT element, The first input of the coupler is connected to the output of the first trigger, and the element I, which is the fact that, in order to increase the accuracy of selection in a given range of durations while ensuring a fixed delay of the output pulse relative to the input and preservation of the duration of the input pulse, the device includes pulse generator pulses, the second delay line, the second AND-NOT element, the differentiation circuit to the delay element, whose input is connected through the differentiation circuit to the input bus of the second line delay and connected to the first input element And, and the output is connected to the reset input of the first delay line, the synchronization input of which is connected to the synchronization input of the second line the clock pulse generator output, the outputs of the first delay line are connected to private reset inputs of the second delay line, the total reset input of which is connected to the output of the And element, the second input of the second one is connected to the output of the second element AND –NE, the first input of which is connected to the inverse output the second trigger, the second input is connected to the output of the first trigger and. the reset input of the second trigger, whose direct output is connected to the second input of the first NAND element, the output of which is connected to the third input of the second NAND element and to the reset input of the first trigger. 2. The selector of claim 1, of which is that the first and second delay lines are executed in the form of shift registers containing A triggers, while the information input of each delay line is connected to the information input of the first the trigger of the corresponding delay line, and the information inputs of the subsequent triggers are connected to the outputs of previous triggers, the sync input of each delay line is connected to the synchronization inputs of the triggers, and the reset input of the first delay line is connected to the reset inputs of the triggers of this delay line , the common reset input of the second delay line is connected to the first reset inputs of triggers of this delay line, the second reset inputs of which are connected to the private reset inputs of this delay line, the outputs of the first delay line are connected to the corresponding triggers of this delay line, and The outputs are respectively t-th and. (nl) -ro flip-flops. Sources of information taken into account at. expertise 1. USSR author's certificate No. 456359, cl. And 03 K 5/18, 26.O9.72 2. USSR Author's Certificate No. 65О224, cl. And 03 K 5/18, 16.06.76 (prototype). srig.2