SU618845A1 - Pulse length selector - Google Patents

Description

one

The invention relates to a pulse technique.

A pulse selector is known in terms of duration, containing two AND elements, an inverter and two pulse formers 1.

The disadvantage of this selector is the inequality of the duration of the output pulses of the duration of the input pulses.

Bo / iee & LIZKY, by its technical nature, is a pulse selector by duration, containing a delay line, an AND element, an AND-NOT element, the first input of which is connected to the device input and the delay line input, the second input - to the output of the delay line and the first the input element and 2.

The disadvantage of this selector is the impossibility of selecting pulses with a duration of both longer and shorter than the set value.

The aim of the invention is to select pulses with a duration both longer and shorter than a predetermined value while maintaining the equality of the durations of the input and output pulses.

The goal is achieved by the fact that the selector impulses in duration, containing a delay line, an element AND, an AND-NOT element, the first input of which is connected to the input of the device and to the input of the delay line ;, the second input - to the output of the delay line and with the first input of the element I, a static trigger is introduced, the first input of which is connected to the output of the element AND-NOT II with the second input of the element AND, the second input is connected to the output of the delay line, and the output is connected to the third input of the element I.

The drawing shows a structural electrical pulse selector circuit for duration.

The pulse selector contains a delay line 1, an AND-NOT 2 element, a static trigger 3 performed on the AND-NO 4 and 5 elements, an AND 6 element. The device has an input 7 and an output 8 and 9. The first input of the AND-NOT element 2 is connected to input 7 of the device and with the input of the delay line 1, the second - with the output of the delay line 1 and the first

the input element And 6. The first input of the static trigger 3 is connected to the output of the element AND-NOT 2 and to the second input of the element 6, the second input is connected to the output of the delay line 1, and the output to the third

the input element and 6.

Pulse selector but the duration works as follows ..

In the initial state, when there is no signal at input 7 of the device, at the output of the delay line 1, the level is n-left, at the RI input of the AND-HE element 2 the unit level. The signal from the output of the NAND 2 element is sent to the first input of the static trigger 3, and the signal from the output of the delay line 1 to the second input of the static trigger 3. At the first output of the trigger 3, which is the first output 8 of the selector, will be set to zero level, (no signal). At the top of the input element And 6, the output of which is the second output 9 of the selector, will also be set to zero, since the output of the delay line 1 is at this moment the zero level.

When a single level impulse arrives at the input 7 of the device, the duration of which iipeBbiniaeT is the delay time of the delay line 1, a zero level impulse is generated at the output of the AND-NOT element 2, which | Th is fed to the first input of a static trigger 3, to the second input of which a single level pulse is applied from the output of delay line 1 at this moment. The zero-level impulse from the output of the NAND gate 2 closes the NAND 4 element, the trigger 3 translates to the one state, while the output of the NAND 4 element is set to a single level, and the output of the NAND 5 element is zero.

The static trigger 3 maintains a single state until the end of the pulse at the output of delay line 1, after which the zero level of the signal from the output of the delay line 1 causes it to become a zero state. At the first trigger output, therefore, a single level pulse is formed at the first selector output, the duration of which is equal to the input pulse duration, and whose temporary position corresponds to the pulse position from the output of delay line 1. At the second output of trigger 3 (at the output of the logic element) -NON 5 at this moment a zero level pulse is formed, the duration and time position of which also corresponds to the pulse from the output of delay line 1. Since during the existence of a pulse at the output delay line 1 on the first and third input element And 6 there is a direct and inverted signal, at its output, which is the second output of the selector, remains zero (no signal). The presence at the initial moment at the second input of the AND 6 element of the zero-level pulse from the output of the NAND element 2 eliminates the possibility of the appearance of short pulses of a single level at the second output of the selector due to the trigger delay of the trigger 3.

Upon arrival at the input of the pulse selector, the duration of which is less than the delay time of the delay line 1 at the output of the element IS-NOT 2 there is no pulse

the zero level, (the unit level is maintained) and the trigger 3 is not translated to the single state. At the output of the element AND-NO 4, the zero level is maintained, i.e., there is no signal at the first output of the device. At the output of the element AND-NE 5 at that moment a unit level is maintained which does not prevent the signal from the output of the delay line 1 from passing through the element 6. At the second output of the device, pulses are emitted in this case,

the duration of which is exactly equal to the duration of the input pulses, and the temporary position corresponds to the position of the pulses at the output of the delay line 1.

The described selector responds to an instantaneous change in the pulse duration, i.e., it distinguishes the duration of two adjacent pulses. For example, if the device received pulses with a duration greater than the specified value, and then

If a single pulse or a series of pulses, the duration of which is less than the set value, has arrived, the first pulse with the duration of the smaller set value will pass to the second output of the device.

If it is necessary to select only pulses, the duration of which is longer than the set value, the element And 6 can be excluded.

Claims (2)

Invention Formula Pulse selector by duration, containing a delay line, an AND element, an NAND element, the first input of which is connected to the device input and to the delay line input, a second input to the output of the delay line and the first input of the AND element, characterized in that pulse selection with a duration of both more and less than a specified value while maintaining the equality of the durations of the input and output pulses, a static trigger is entered into it, the first input of which is connected to the output of the NAND element and to the second input of the AND element, the second input is connected to the output of the delay line, and the output is connected to the third input of element I. Sources of information taken into account in the examination: 1. USSR author's certificate L 409361, class H 03 K 5/20, 04.01.72. 2. USSR author's certificate L 444317, cl. H 03 K 5/18, 07.28.72.