SU921070A1

SU921070A1 - Pulse duration discriminator

Info

Publication number: SU921070A1
Application number: SU802954888A
Authority: SU
Inventors: Владимир Пантелеевич Баклан; Михаил Владимирович Левданский
Original assignee: Предприятие П/Я А-3327
Priority date: 1980-07-10
Filing date: 1980-07-10
Publication date: 1982-04-15

Description

(5) СЕЛЕКТОР ИМПУЛЬСОВ ПО ДЛИТЕЛЬНОСТИ(5) PULSE SELECTOR FOR DURATION

II

Изобретение относитс к импульсной технике и может быть использова но в дискретных устройствах автоматики .The invention relates to a pulse technique and can be used in discrete automation devices.

Известен селектор импульсов по длительности, содержащий элемент задержки , элемент И-НЕ, элемент И и триггер СП.Known selector pulses in duration, containing the delay element, the element AND-NOT, the element And the trigger SP.

Недостатком известного селектора вл етс низка надежность его рабо- ты.A disadvantage of the known selector is the low reliability of its operation.

Наиболее близким по технической сущности к изобретению вл етс селектор импульсов по длительности, содержащий триггер, единичный вход которого соединен с выходом первого элемента И, нулевой вход через первый элемент НЕ соединен с выходом элемента ИЛИ, пр мой выход подключен к первой выходной шине, а инверсный выход - к первому входу второго элемента И, второй вход которого соединен с выходом элемента задержки и первым входом первого элемента И и сThe closest in technical essence to the invention is a pulse selector in duration, containing a trigger, a single input of which is connected to the output of the first AND element, a zero input through the first element is NOT connected to the output of the OR element, the direct output is connected to the first output bus, and the inverse output - to the first input of the second element And, the second input of which is connected to the output of the delay element and the first input of the first element And and

первым входом элемента ИЛИ, второй вход которого соединен с входной шиной , вторым входом первого элемента И, входом элемента задержки и через элемент НЕ - с третьим входом второго элемента И, выход которого I соединен с второй выходной шиной 23.the first input of the OR element, the second input of which is connected to the input bus, the second input of the first element AND, the input of the delay element and through the element NOT to the third input of the second element AND whose output I is connected to the second output bus 23.

Недостаток известного устройства низка надежность работы.A disadvantage of the known device is low reliability.

Цель изобретени - повышение на10 дежности селектировани .The purpose of the invention is to increase the reliability of selection.

Цель достигаетс тем, что в селектор импульсов по длительности, содержащий триггер, единичный вход которого соединен с выходом первого The goal is achieved by the fact that, in the pulse selector, by duration, containing a trigger, a single input of which is connected to the output of the first

15 элемента И, нулевой вход через первый элемент НЕ соединен с выходом элемента ИЛИ, пр мой выход - с первой выходной шиной, инверсный выход - с первым входом элемента ИЛИ, второй 15 element AND, zero input through the first element is NOT connected to the output of the element OR, direct output to the first output bus, inverse output to the first input of the element OR, second

Claims

The 20 input of which is connected to the input bus, the first input of the first element I, the input of the delay element, and through the second element NOT to the third input 39 of the second element AND whose output is connected to the second output bus, the third element AND and the additional delay element are entered, the input of which is connected to the output of the delay element and the first input of the third element AND, the second input of which is connected to the output of the additional delay element and the first input of the OR element, and the output to the second input of the first element I. In FIG. 1 shows a block diagram of the device; in fig. 2 time diagrams for his work. The device contains a trigger 1, elements 2 and 3 delays, elements A, 5 and 6 AND, element 7 OR, elements 8 and 9 are NOT .. The numbers 10, 11 and 12 denote input, first output and output bus number two. The pulse selector in duration works as follows. In the initial state, in the absence of a signal on bus 10 at the inputs and outputs of elements 2 and 3, at the inputs of elements +, 5, 8, 9 unit potentials are absent, therefore there are zero potentials on the elements 5, therefore trigger 1 is in the single position is not established, and the unit potential from the output of element 8 keeps trigger 1 in the zero state, since it is fed to the input of the trigger setup in the zero state. At the inverse output of the trigger 1, there is a single potential that is fed to the first input of element 6, and a second potential is applied to the second input of element 6, therefore, at its output, which is the second output of the device, there is no signal. When a selector signal reaches the bus 10 selector, the duration of which is longer than + t2, where C is the delay time on element 2, tj is the delay time on element 3, on the output of the element (see Fig.2, g a signal appears, duration from the leading edge of the signal from delay element 3 (see fig. 2 c) to the falling edge of the signal from delay element 2 (see fig. 2, b), which goes to the second input of element 5 and allows the passage of a high level at the output of the element 5 (see Fig. 2). Thus, the input of the trigger 1 to 1 sets a high potential l, which means that on the first output bus 11 there is a unit-level Wits pulse (see Fig. 2, whose length is equal to the duration of the input pulse, and the temporary position corresponds to the position of the pulse at the output of the 3 element. the duration of the input pulse with a follow-up period commensurate with the total delay time t, the signal for setting trigger 1 at the output of element 5 (see Fig. 2, d) does not appear, since the delayed signal of the interference pulse is present at the output of element 3, at the input of element 2 and at the first input of element 5, on the second input of which there is no signal, due to the fact that element k is locked, so as at the output of element 2 there is no signal. No signal is received at the single trigger input and false positives do not occur. Thus, this invention makes it possible to increase the reliability of the pulse selector in terms of its duration due to its protection from the action of a series of impulse noise. Claims of the pulse duration selector containing a trigger, the single input of which is connected to the output of the first element AND, the zero input through the first element NOT to the output of the OR element, the direct output to the first output bus, and the inverse output to the first input of the element OR whose second input is connected to the input bus, the input of the delay element, the first input of the first element AND, and through the second element NOT to the third input of the second element AND whose output is connected to the second output. bus, characterized in that, in order to improve the reliability of selection, a third AND element and an additional delay element are inputted into it, the input of which is connected to the output of the delay element and the first input of the third AND element, and the output to the first input of the OR element and the second input of the third ale

59210706

ment And, the output of which is connected c1. USSR authorship

the second input of the first element I. (G 6l88l5, cl. I03 K 5/26, 1977. Sources of information,

2. USSR author's testimony

taken into account with exporter-jojo no. 666637, cl H03 K 5/26, 1977iff 9 rcpu froMex

Fig2