SU748841A1 - Pulse timing device - Google Patents

Description

-. ,, - The invention relates to automation and computing and can be used in devices for discrete information processing.

A synchronization device of 5 pulses is known, which contains a trigger, ele,. cop OR, two elements AND NOT and element

And i. . . .....: ;;; .--:.:;:

The disadvantage of this device is that the duration of the synchro-0 pulse must be shorter; above the period of the following clock pulses. . . . .: V:,;} :::

The closest to the technical essence of this invention is a device for synchronizing um pulses, containing a trigger and four AND-NOT elements, the output of the first AND-NOT element being connected to. the first input of the second element of the NAND, whose input is connected to the first inputs of the first and third elements of the NAND, the output of the third element of the NAND is connected to the first input of the fourth element 25 of the NAND, whose output is connected to one of trigger inputs 2.

The disadvantage of this device is the narrow scope, since at the time of forming the synchronization

The device does not impose a pulse: it prevents the formation of clock pulses, which makes it impossible to apply it in information processing systems where it is necessary at the time of forming a synchronized (control) pulse to prevent the formation of clock pulses. . ;

The purpose of the invention is to expand the functionality. ,

This goal is achieved by the fact that in the device containing the Trigger and the four elements NAND, and the output of the first element NAND is connected to the first input of the second element NAND, the output qcddrgo is connected to the first inputs of the first and third elements I and NN whose output is connected to the first input of the fourth NAND element, the second input of which is connected to the second INPUT of the first NAND element and to the clock bus, and the output: connected to one of the trigger inputs, the second input of which is connected to the bus input pulses, trigger output with of the connections to the second input of the second AND-NO element, an output of fourth AND-NO element is connected to the third WMOs: house the first and second input of the third AND-NO element. FIG. 1 is a block diagram of the device; in fig. 2 - time diagram of his work. The device circuit contains trigger 1, elements 2, 3, 4,, 5 AND –NE bus 6 clock pulses, bus 7 - input pulses, output bus 8, 9. Trigger 1 has a direct dynamic unions input and static static zero input. Trigger 1 switches to one state by; the leading edge of the input, impulse, input; a dynamic single input to the eGSE; the zero state, three Ger, switches when its zero input reaches the logical zero level, independently of the single input state. For the construction of such a trigger, it may be; ibpolzrvan, for example, 1 - trigger Tj. ria 133TM2, 13bTmg, 155TM2. To do this, its T) - and S-inputs need to understand the voltage of the logical unit. In this case, the C-input of the trigger uses icaK unit dynamic input, and the R-input as the zero inverse input .. the output of element 2 is NOT connected to the first input element 3 AND-NOT, whose yhshed is connected with Pervysh input elements 2- and 5 AND-NOT. The output of the element .5 and -NON is connected to the first input of element 4 AND-NOT, the output of which is connected to the second inputs of elements 2 and 5 X-NOT. And zero input of the trigger 1 whose output is connected to the second input of the element a 3 AND-NOT , and a dynamic single input with bus 7. The bus b connects the third input of element 2 and the second input of element 4 AND –NE. The output bus 8 and 9 are connected respectively with the outputs of the elements 2 and 4 AND-NOT. The device works as follows SOM. . .... In the initial state, bus 7 contains a zero logic level, and clock pulses arrive on bus 6. At the outputs of elements 3, 4 AND-NOT there are single logical levels, and at the outputs of trigger 1 and element 5 AND-Y, logical zero levels. At the output of element 2. AND-NOT (bus 8) inverted clock pulses are formed .. -. . ; .-. . -. . Pusf input impulse arriving on the bus 7 in the interval between clock pulses (t In Fig. 2). On the leading front of the input pulse, trigger 1 is interleaved and its output is given by the level of the logical unit. As a result, at the output of element 3 AND-NOT, a zero logic level is formed, which is fed to the output of Alemite 2 AND-NOT and prohibits the passage of a clock pulse on bus 8. At the same time, a single logical level is formed on the view of element 5 H-NOT allowing the clock pulse at the output of element 4 (bus 9) .. When a clock pulse arrives on bus 6 (t2 in Fig. 2), an inverted clock pulse arriving at the zero output of trigger 1 is generated at the output of element 4 AND-NOT. Trigger 1 switches to the initial one ( zero) sos This, and at its output, forms a zero logic level, which enters the input of element 3 AND-NOT. At the output of element 3. AND-NOT, a UNIQUE LOGIC level is formed, which enters the entry of element 2 AND-NOT. However, the impulse to the output of the element 2. AND-N.E will not pass, - as it is blocked And p6way zero logic level coming from the output of the element 4 AND-NOT. At the end of the clock pulse at the output of the element 4 AND-NOT, a single logical level is generated, which enters the Inputs of the elements 5 and 2 and-HE, as a result of the output. element 5 AND-NOT is set to zero logic level, prohibiting the passage of clock pulses and entry element 4. AND-NOT .. (bus 9). V A single logical level coming from the output of element 4 AND-NOT to the input of element 2 AND - NOT allows the passage of clock pulses to the bus 8. Thus, the device returns to the Initial state. . In the timing diagram of the Illustrator also, the case where the input signal arrives on bus 7 at time. the action of the clock pulse (tj in FIG. 2). In this case, the device waits for the end of the clock pulse, and for: it works similarly to the case. Thus, when the input pulse arrives on the device bus 9, a pulse synchronous with the clock pulses is generated, the incoming bus 6 simultaneously from the sequence of clock pulses generated on the bus 8, the pulse corresponding to the timing pulse is eliminated. - The device can only be used to generate synchronized pulses, WO also in TaJc. Case, when it is necessary to separate. Lei: p1 in time clock. Himggulsy. (pulses ya shiye 8) and. syngfoyieirovaniyy impulses (impulses on rank 9). This makes it possible to refuse. | eide. cases from application of multiphase and synchronization, use; which is associated with: an increase in hardware costs; In addition, the application. Single-circuit devices for the formation of synchronous pulses, as well as for the separation in time of synchronized and clock-based impulses of instrumentation and hardware design and simplifies maintenance.

Claims (2)

1. Authors certificate of the USSR 434581, cl. NOZ K 5/00,: 21.02. 2. USSR author's certificate №544120, cl. H 03 K 5/156. 17.M, 75. П П1 П П П П П Ш.и, на.б phage. / Yu P P P P