SU741436A1 - Noise suppression device - Google Patents

Description

one

The invention relates to a pulsed technique and can be used in telemechanics and discrete automation devices for receiving signals under the conditions of impulse noise,

A known noise suppression circuit comprising two triggers, an AND circuit, an OR 1 circuit.

For stable operation of this circuit, the duration of the gating pulse is up to less than the response time of the three gates, otherwise the impulse noise from the input goes to the output of the circuit as a full-fledged pulse. Since the valve response times vary widely, from the sample to the sample and depending on the temperature conditions, it is necessary to apply special measures for adjusting the gate pulse duration. The choice of the duration of the gate pulse by the minimum valve response time is almost impossible to accomplish due to the high speed of the valves.

The closest in nature to the invention is a pulse shaper, -containing two trig, hera, two coincidence circuits, an inverter, a paraphase pulse 2.

A disadvantage of this device is low noise immunity under the conditions of multiple pulse interference 4. If two interference pulses coincide with two pulses of one period of a paraphase generator, then such interference is perceived as a signal and

10 a full pulse appears at the shaper output.

The aim of the invention is to improve the noise immunity of the device. va.

15

This is achieved by the fact that in a device containing two triggers, an inverter, two coincidence elements, the input bus connected to the first input of the first match element and the input of the inverter, whose output is connected to the first input of the second matching element, and the outputs of the first and second matching elements connected to inputs S and R of the first trigger

25, respectively, the output of the first flip-flop is connected to the D-input of the second flip-flop, the first output of the second flip-flop is connected to the second input of the first coincidence element, the second output

30 of the second trigger with the second input of the second coincidence element D D - the input of the first trigger is connected to the input bus, and the inputs of the first-o and second triggers are connected to the clock pulse bus. The drawing shows a block diagram of a noise suppression device. The device contains an inverter 1, elements 2, 3 coincidence, triggers 4, 5. The device input bus b is connected to the input of the inverter, to the D input of the trigger 4 and to the first input of the coincidence element 2, the output of which is connected to the S input of the trigger 4, and the second input is connected to the first output of three gres 5. The output of the inverter is connected to the first input of element 3, the output of which is connected to the K input of trigger 4, and the second input to the BIN output of the trigger 5. Bus 7 clock pulses connected to the control inputs of the trigger 4 and 5, and the output 8 of the device is connected to the first oy go trigger 5, the D-input of which is dinane with the trigger output 4. The device operates as follows. On the bus b device receives input signals on the bus 7 - clock pulses. The initial state of the triggers 4 and 5 is zero. With the presence of a zero-level bus 6, with each clock pulse frequency on bus 7, the status of the triggers is confirmed. When a high level appears on the bus (a pulse appears at the input of the device). At the leading edge of the clock frequency pulse, the trigger is set to Input B-Trigger-5 receives a high potential from the output of trigger 4, however, there is no change in the state of the trigger 5, since the signal at its D-input is delayed relative to the signal on the control to the cement input. With the arrival of the second pulse of the clock frequency, the trigger 5 is set to H and a signal appears at the output 8 of the device. As soon as the signal at input b becomes equal to zero, the arrival of the first pulse of the clock frequency triggers 4, set to O, and when the second pulse arrives, it sets to O, trigger 5, and the signal at output 8 of the device decreases. whose high level coincides with the clock frequency pulse, trigger 4 sets to 1. As soon as the interference level becomes zero, trigger 4 through inverter 1 and coincidence element 3 is set to the zero state. With the arrival of the second clock pulse, the trigger 5 does not change its state, i.e. the interference at the device input does not pass to the output. This also applies to multiple impulse noise at the input of the device. The device responds only to an input pulse, the duration of which intersects the leading edge of two clock pulses. The duration of the output signal is defined. is the duration of the input signal. The device also selects impulse noise /, which is superimposed on a high level of the input signal and leads to a short-term establishment of the input signal. After the establishment of trigger 5, i, the resolving potential at the input of the coincidence element 3 is removed and the resolving potential is fed to the input of the coincidence element 2. If the setting in O of the input signal as a result of the interference does not coincide with the clock pulse, then the change in the state of the trigger 4 and, accordingly, the trigger 5 does not occur, since the circuit 3 does not match. If the hindrance sov-. falls with a clock pulse, trigger 4 is set to -O. As soon as the input signal level is restored when the interference stops, trigger 4 is set via a matching element 2. The output signal is set to O only when there is no input signal in the time interval that overlaps the leading edge of two consecutive clock frequency pulses. In the known device, the state of the flip-flops changes at the moments of arrival of the clock frequency pulses, and in the pauses it remains independent of the state of the input signal. Therefore, multiple impulse noise, in which two pulses coincide with the clock frequency pulses, is perceived as a full-fledged input signal. In the proposed device, changes in the state of triggers also occur at the moments of arrival of clock pulses, however, in the pauses between them when the state of the input signal changes, the first trigger recovers its state, thus neutralizing the adverse effect of the preceding pulse interference. Thus, the proposed device provides for the selection of both single and multiple impulse noise, i.e., it has a higher noise immunity compared to known devices. In addition, the operation of the known device requires a special generator of paraphase signals and an essential initial signaling device that is new. In the absence of installation

it is possible to issue signals from

at

first interference, since when the power is turned on, the trigger can be set to any state. For the operation of the proposed device, it is sufficient to have a single-cycle pulse generator and does not require pre-installation in a special signal, i.e., application of the proposed device is associated with less technical difficulties as compared with the application of the known device.

Claims (2)

Invention Formula An interference suppressor comprising two triggers, an inverter, two coincidence elements, the input bus connected to the first input of the first matching element and the input of the inverter, the output of which is connected to the first input of the second element coincident {| and, and the outputs of the first and second matching elements are connected to the inputs S and R of the first trigger, respectively, characterized in that, in order to improve the noise immunity, in it the output of the first trigger is connected to b by the input of the second trigger, the first output of the second trigger is connected to the second input 4 of the first element of coincidence, the second output of the second trigger - with a second input of the second coincidence, iD -Log first flip-flop "is connected to the input br Nye, and control inputs of the first and second flip-flops are connected with the bus clock pulses im5. Sources of information taken into account in the examination of. For the UK 1473706, CL. H 03 K 5/18, 1976. 0 2. USSR author's certificate 437203, cl. H 03 K 5/01, 1972.