SU1517123A1 - Pulse shaper - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices. The purpose of the invention — enhanced functionality — is achieved by additionally generating paired single pulses. The pulse shaper contains the triggers 1,2 and 3, the gates 4 and 5, the bus 6 clock pulses, the bus 7 control, output tires 9 ÷ 11. The second and third triggers are made of JK-type with the corresponding functional connections between them. The D-type trigger was used as the first trigger. 1 il.

Description

ate

vl

N0

00

The invention relates to a pulse technique and can be used in automation and computing devices.

The purpose of the invention is the expansion of functional capabilities due to the additional formation of paired single pulses

The drawing shows the electrical functional scheme of the device

The delay pulse shaper contains the first 1, second 2 and third

3 triggers, the first 4 and second 5 valves, the 6 clock pulse bus, the control bus 7 and the first to fourth output buses 8 to 11. First trigger 1 and-type, second 2 and third 3 JK-type triggers. The bus 6 clock pulses is connected to the C inputs of the first to third triggers 1–3 and to the first input of the 1st valve 4, the second input of which is connected to the K and S inputs of the third trigger 3 and to the direct output of the second trigger 2, inverse the output of which is connected to the J-input. the third trigger 3 and with the S input of the first trigger 1, the D input of which is connected to the control bus 7 and to the K input of the second tripper 2, the J input of which is connected to the inverse output of the first trigger 1 and the first output bus 8; the second output bus 9 is connected to the output of the first valve

4 and with the first input of the second valve 5, the output of which is connected to the second output bus 10, the second input with the direct output of the third trigger 3 and the fourth output bus 11

The pulse shaper works as follows

In the absence of a signal on bus 7 (logical 1 present), triggers 1 and 3 are in one state, in which the direct outputs of these triggers have a logic level 1, and on inverse outputs a logic level O, trigger 2 is in zero state in which, at its direct output, the logic level O, and at the inverse level, the logic level 1, the unit state of the trigger 1 and the zero state trigger 2 are provided by impulses from the bus 6, and the unit state of the trigger 3 direct output trig hera 2 to the S-input of the trigger 3, this level blocks the passage of pulses from the bus 6 to the output of the valve 4 and the bus 9; the zero signal from bus 9 blocks the passage of the signal to the output of the valve 5 and to the bus 10. At the inverse output of trigger 1 and on bus 8 there is a logic level

When a signal appears on bus 7

the logic level O on the nearest leading edge of the pulses from bus 6 switches trigger 1 and on bus 8 appears the level of logic I. This signal enters J-input of trigger 2 and on the nearest falling edge of pulses from bus 6 trigger 2 switches, producing a signal logical O to the S input of the trigger 1 and drive it to its original state, and

the logical signal to the second input of the valve 4 and to the K input of the trigger 3. Thus, the output of the valve 4 and the bus 9 passes pulses from the bus 6 and the output of the valve 5 and on the bus

10 a second output pulse appears

On the next falling edge of the pulse from the bus-6, the trigger 3 switches to its initial state, and after the signal on bus 7 (on the falling edge of the pulse from bus 6) finishes, the trigger 2 returns to its initial state, prohibiting the passage of pulses to the bus 9 and driving to initial state trigger

35

Claims (1)

Invention Formula Pulse shaper containing the first trigger, inverse output which is connected to the first output bus, C input is connected to the clock pulse bus and to the first input of the first valve, the output of which is connected to the second output bus, the second and third triggers, the second valve, the third output bus and the control bus, differing in that in order to extend the functionality due to the additional forming a pair of single pulses, in it the second and third triggers are made of JK-type and a fourth output bus is inserted, moreover, the control bus is connected to the D-input of the first trigger and to the K-input of the second trigger, the J-input of which is connected to the inverse output of the first trigger which is connected to the J-input of the third trigger and inverse you 5 15171236 the second trigger, the C input of which the output of which is connected to the first is connected to the second bus clock named after the second valve, the output of which pulses and with the C-input of the third trigger-connected to the third output bus, Hera. The K- and S-inputs of which are connected - the second input - with the direct output is tertiary with the Direct output of the second trigger of its trigger and with the fourth output and with the second inlet of the first valve bus.