SU1223228A1 - Device for detecting and subtracting the first pulse from pulse sequence - Google Patents

Abstract

The invention relates to computing and allows for improved reliability. The device contains a bus 1 reset pulses, bus 2 input pulses, output buses 3 and 8, triggers 5, 9, 12 and 15, each of which consists of two logical elements AND IS NOT 6 and 7, 10 and 11, 13 and 14, 16 and 17. The device extracts from the sequence of pulses fed through a cord 2, the first full positive pulse after a transition from the Zero state to a single reset pulse. A selected pulse is formed on the output bus 8. On the bus 3, an input pulse sequence is formed, from. which excludes pulses emitted on the output bus, 8. 2 Il. (L with 1C 1C with 1C N9 oo

Description

The invention relates to a pulsed technique and can be used in computing devices.

The aim of the invention is to increase the reliability of operation.

Fig. 1 is an electrical circuit diagram of a device for extracting a first pulse and subtracting the first pulse from a sequence of pulses; in fig. 2 - time diagrams of the device operation (the number of the diagram corresponds to the number of the element from the output of which the corresponding diagram is taken).

The device contains a tons of 1 reset pulses, a bus 2 input pulses, a second output bus 3 connected to the output of a three-input logic element AND-NOT 4, one of the inputs of which is connected to the bus 2 input pulses, the first trigger 5 of two elements AND-HE 6 and 7, and the output of the element IS-HE 6 is connected to the first output bus 8, the second trigger 9 of two logical elements is AND-NOT 10 and 1, and the zero input of the trigger 9 is connected to the bus 1 of the reset pulses, the third trigger 12 with two unit installation inputs consisting of two elements AND-NOT 43 and J4, The first input of the trigger unit is connected to the bus 1 of the reset pulses, and the zero input to the bus 2 input pulses, the fourth trigger 15 to the three installation inputs of the unit, consisting of two elements AND NOT 16 and 17, and the first input of the installation the trigger unit is connected to the bus 2 input pulses, and the input of the zero setting is connected to the single output of the second trigger.

The device extracts from the sequence of pulses fed through the bus of the input pulses, the first full positive pulse after the transition from the zero to one state on the bus of the reset pulses. A dedicated pulse is generated on the first input bus of the device. On the second output bus, an input pulse sequence is formed, which excludes the pulses produced on the first output bus.

The device works as follows.

At the initial moment of time t

giving a low potential to the bus 1 reset pulses, on the bus 2 input pulses there is an input pulse,

causing the formation of a zero potential on the second output bus 3 of the device (the output of the element is NOT 4). This corresponds to the unit potential at the unit output of the first trigger 5, which is formed at the output of the NAND element 6, and the zero signal at the zero output of the trigger 5 (the output of the element NAND 7). Since the first output bus 8 is connected to the output of the element, NAND 6, then at the initial moment of time a single signal is formed on the first output bus 8. The second trigger 9 at the initial moment of time is in a single state: a single signal is present at the single output (output of the NE-NE element 10), and a zero signal at the zero output (output of the AND-NO element). The third trigger er 12 at the initial moment of time is also in the unit state: at its single output (output of the NAND 13 element) there is a single signal, and at the zero output (output of the AND-NOT 14 element) it is zero. As well as the first three triggers, the fourth trigger 15 at the initial moment is in a single state, its single output (output of the element AND-NOT 16) has a single signal, and at the zero output (output of the element AND-NOT 17) - zero.

After a low, zero potential applied to the bus 1 at the initial moment of a reset pulse, a high potential is generated at the output of the NAND 11 element, which, in turn, causes the appearance of a low signal at the output of the NAND 10. This low potential forms a single the signal at the output of the NAND 17 element. However, this signal is applied to the inputs of the NAND elements 13 and 16, to the other inputs of which a low potential is applied from the bus 1 of the reset pulses. Therefore, other changes in potentials at the initial moment does not occur.

Let at the moment, t, the potential on the bus 2 input pulses become low. After that, at the outputs of the AND-HEY elements 14 and 4 (the second output - bus 3) a high voltage level is formed. No other signal changes at tf time.

After that, at time t, a high potential arises on bus 1 of reset pulses, which leads to the establishment of a low signal at the output of the NAND 13 element. There are no other changes in the signals from the outputs of the elements at time tj,

At the moment of the beginning of the first positive pulse on bus 2 of the input pulses after the occurrence of the transition from zero to one state on bus 1 of the reset pulses (t) a low potential is formed at the output of the I-NE element 16. This potential causes a high level appearance. on the outputs of the logical elements AND-NOT 7 and 10. After the formation of a high potential at the outputs of the elements 7 and 10, there are unit potentials at both inputs of the elements AND-HEN 6 and 11, and a zero signal appears at the outputs of the elements 6 and P . There will be no other changes in signals at the outputs of logic elements at time tj. Thus, at time i, a low potential is formed on the first output shida 8 (output of the AND-NOT 6 logic element). This low signal is maintained at the first output bus 8 until the moment t of the end of the positive pulse on the bus 2 input pulses.

At the moment t, the low potential on the bus 2 of the input pulses establishes high potentials at the outputs of the NAND logic gates 16 and 6 (first: output bus 8). After this, low levels of signal-signals are formed at the outputs of the AND-NOT 7 and 17 logic elements. A low potential at the output of the logic element J7 generates a high signal at the output of the AND-NOT element J 3. There is no other change in signals at the instant of q. Thus, at time t, all high potentials are formed at the output of the AND-HE elements 14 and 4, with the exception of the bus 2 input pulses at a high potential level on bus 1 pulse reset, the device executes pulses on the second bus 3 output pulses.

At the instant tj of the common-mode low potential on bus 2 of the input pulses, the signal on bus 1 becomes low. This signal causes the formation of a high potential at the output of an AND-HI element 11, which, in turn, generates a low signal at the output of the N-10 element. Thereafter, a high signal appears at the output of the H-element 17. Thus, at all inputs of the elements AND-NOT 14 and 4, except inputs,

connected to the bus 2 input pulses, high signals appear, and inverted pulses from the bus 2 input pulses are generated at the outputs of these elements. The formation of these

pulses lasts until a high signal appears on the pulse bus I bus. Let that high signal to shi. not 1 in phase to a single level. voltage on the bus 2 input pulses

at time t (the formation of a high signal on bus 1 in phase with the zero level on bus 2 is considered above - at time t).

At the moment ty of the first after the moment tg of establishing a low potential on the bus 2 of the input pulses, high potentials are set at the outputs of the AND-HES 14 and 4 logic elements (second output bus 3). After

forming a high signal at the output of the NAND 14 element appears a low signal at the output of the NAND 13 logic element. There will be no other changes in the signals on the output of the elements at the time t. Thus, at the time t, the device turned out to be in the same state as at time t n further, the operation of the device is repeated.

Let after the beginning of the pulse on the tire 8, when, similarly

the moment t, the signals at the outputs of the elements AND-HEY 16, 6 and 11 change to zero, and the signals at the outputs of the elements 7 and 10 change to single, a low voltage level is formed

on bus 1 pulse reset (MOMeHT tg). At the moment, a low signal on bus 1 sets the high potentials at the outputs of the NAND logic gates 11, 13 and 16. At both inputs

the logical element AND-NOT J4 turns out to be high signals (from the bus 2 input pulses and from the output of the element IS-NOT 13), thus, at the output of the element AND-HE 14 a potential of zero is formed. High signals from the outputs of the logical elements AND-NOT 16 and 11 cause the appearance of a low signal at the output of the logical element AND-NOT 10. After forming a high signal at the output of the element AND-NOT 16 and before forming a low potential at the output of the element IS-NOT 10 output element AND-NOT 17 can

show a short-term negative release. However, the output of the element AND-NOT 17 is connected to the inputs of the elements AND-NOT 13 and 16, the output signals of which | this short-term burst cannot be changed; at the outputs of the elements, there is a previously formed low potential from the bus 1 of the reset pulses. Other changes of signals at the moment tg will not occur.

A high signal on bus 1 reset pulses appears before a low potential is formed on bus 2 input pulses. Since bus 1 is connected to logic elements 11J 13 and 16, at the outputs of which there are low potentials (for element AND-HE 11c the output of element AND-NO O, and for element AND-HE 13;: and 16 - from the output of element Y-NOT 14), the appearance of a high potential on bus 1. Reset pulses does not change the output potentials of any logical element of the device. They remain unchanged until the moment t of the appearance of a low potential on the bus 2 input pulses.

At the moment ty, the low potential on the bus 2 input pulses to the formation of single signals at the outputs of the logical elements IS-NOT 6 (first bus 8) and 4. A high signal from the output of the element IS-NOT 6 causes the appearance of a low signal at the output during the logical element AND-NOT 7, and a high signal from the output of the element AND-NO 14 sets a low potential at the output of the element AND-NOT 13. There will be no other changes in the output signals of the device elements at time t and, therefore, all signals on the outputs of the logic elements coincide with the signals set Hb w at time tj. Further, the operation of the device for extracting the first pulse and subtracting the first pulse from

of validity with.

pulses repeat q

j 0 5

50

five

0

Claims (1)

Formula of Invention A device for measurement and calculation. The first pulse from a pulse sequence containing two asynchronous triggers with separate inputs, executed on two AND – NOT elements, the single input of the first trigger connected to the input pulse bus, and the single output from the first output bus, zero input of the second trigger connected to the bus reset pulses, characterized in that, in order to increase the reliability of operation, the third trigger on two AND-NOT elements with two single inputs is entered into it, the fourth trigger on two AND-NOT elements with three single inputs AMI and three-input element IS, NOT, and the zero output of the third trigger is connected to the first single input of the fourth trigger, the zero output of which is connected to the first single input of the third trigger, the second single input of which is connected to the second single input of the fourth trigger and zero input of the second trigger, single the output of which is connected to zero at the input of the fourth trigger, the unit output of which is connected to the single input of the second trigger and to the zero input of the first trigger, whose single output is connected En to the first input of the three-input element IS-NOT, the output of which is connected to the second output bus, and the second input is connected to the bus of input pulses, the third single input of the fourth trigger and the zero input of the third trigger, the unit output of which comes off the third input of the three-input element I- NOT. -