SU864529A2 - Shaper of single pulses synchronized by clock frequency - Google Patents

Description

(54) FORMER OF SINGLE PULSES,

SYNCHRONIZED CLOCK FREQUENCY

The invention relates to a pulse technique and can be used to temporarily lock signals into

. Automation devices .i. computer technology, carried out the exchange of information at an asynchronous rate.

According to the main auth. No. 552687 is known a single pulse driver containing input and calling one triggers, first, second, third elements and, respectively, interconnected. The use of a known driver allows you to receive single pulses from the leading edge of the input signal with reference to the clock frequency of the device. OUT SYNCHRONIZED CYCCH pulses. The shaper does not provide synchronization of input pulses by duration, when the input signal, the duration of which is less than the follow-up period — clock pulses, starts at the moment of low, and ends at, the moment of high frequency of clock pulses, or the input signal, duration

which is less than the duration of the high level of the clock pulses, begins and ends at the time of the high level of the clock frequency pulse. In these cases, the driver generates short output pulses, the duration of which is determined by the total response time of the input trigger and the two elements I. If the input signal starts and ends at the moment of the presence of a low level of the clock frequency pulse, the driver does not respond to it. The presence of such conditions limits the applicability of the former.

The purpose of the invention is to ensure stable operation of the driver for any duration of the input signals.

The goal is achieved by the fact that the driver of single pulses synchronized with a clock frequency contains input to output triggers and three elements AND, the first input of the input trigger is connected to one of the inputs of the first element And, the other input of which is connected to one of the outputs of the input trigger, The first element of the first element is connected to the first input of the output trigger, the output of which is through the second element and connected to the second input of the input trigger, the second output of which is third to the third element of the second The Rome input of the output trigger, the first input of which is connected to the first emitter of the second element I, the output of the third element I is connected to the additional input of the second element AND, enter the additional trigger, the first input of which is connected to the bus of input signals, the second input to the output of the second gate And, and the output is connected to the first input of the input trigger. Figure 1 shows the functionality of the electrical circuit; 2 a temporal diagram of operation of the former. The shaper is implemented on potential elements and contains (FIGS. 1 triggers 1-3, logic elements AND 4-6, input bus 7, clock clock 8 impulses, and single pulse single bus 9. In figure 2, the positions are: 10- input signals of the imager on bus 7, 11 - clock signals on bus 8, 12 - signals at the output of the trigger 1, 13 - signals at the output of the trigger 2, 14 - signals at the output of the logic element 4, 15 signals at the output of the logic element I 5, 16 - signals at the output of the trigger 3, 17 - signals at the output of the logical element And 6, P The first trigger input 1 is connected to the input signal bus 7, the second input is connected to the output of the logic element 5, to the second input of the trigger 3 and one of the inputs of the logic element 6, and the output to the nepBOMS trigger 2 and 4 , the first input of which is connected to the bus 8 of the clock pulses and the first input of the element 5, the third input is connected to the first output of the trigger 2. The output of the element 4 is connected to the first input. trigger house 3 and the first input element AND 6, the second input of which is connected to the trigger output. 3, and the output bus 9 and the second input of the trigger 2. The second output of the trigger 2 is connected to the second input element And 5. The shaper works as follows. The absence of a signal on the input bus 7 (Fig 2.10) allows the clock pulses through the AND b And 5 elements to convert the triggers 1 of Figs 2,12 ii 3 of Figs 2,16) to the zero state, resulting in a low level the signal from the output of trigger 1 converts Trigger 2 (FIG. 2,13) into one state and at the same time prohibits the passage of a high level signal from the first output of trigger 2 through Element 4. The high level of the input signal of any duration on bus 7 (FIG. 2 , 10) sets the trigger 1 (FIG. 2, 12) S to a single state and allows the signal to pass from th output of the trigger element 2 through 4 and in the presence at its first input the high level clock pulse. In this case, at the output of the AND 4 element (Fig. 2,14), the logical Koro zero signal translates the trigger 3 (Fig. 2, 16 into one state and at the same time prohibits the passage of a high level signal from its output through the And 6 element. On admission to the first input element And 4 low level pulse clock frequency at the output element And 6 (figure 2, 177 forms a low level signal, which is fed to the bus 9, and also switches the trigger 2 Ffg 2,13) in the zero state. Low level signal from the first output of trigger 2 prohibits the repeated operation of the element 4, and a high level at the second output of trigger 2 prepares the triggering of the element 5 after the formation of the output pulse completes. The occurrence of a high level of the clock frequency on the bus 8 (Fitz, 2.11) ensures that the trigger 3 (Fig 2,16) translates into the zero state through the element And 5. The low level of the signal from the output of the trigger 3 prohibits the formation of an output pulse on the bus 9. On the second, the input of the trigger 1 begins to receive signals of a low level from the output of the element And 5. (Fig.2.15) at the clock frequency until Wits on its first input signal is low level, as a result. trigger 1 Fig, 2,12) is set to zero, and trigger 2 (Fig. 2,13J - to one state). The high level of the signal from the first trigger output 2 allows the formation of an output pulse when the next input signal arrives. The former is in its initial state and is ready to form a single pulse. Thus, the introduced additional trigger remembers the input signals of any duration and keeps the signal high at one of the inputs of the AND 4 element until the end of the output pulse. This eliminates the false triggering of the AND 4 element, therefore, allows to receive single pulses from the leading edge of the input signal of any duration on the output bus with reference to the clock frequency. The shaper ensures stable operation in any range of the duration of the input signals, and the duration of the output pulses is always equal to the duration of the synchronizing pulses.

Claims (1)

1. Shaper single pulses, synchronized clock frequency, auth.St. No. 552687, characterized in that, in order to ensure stable operation, for any duration of input signals, an additional Iljl the trigger, the first input of which is connected to the bus of input signals, the second input - to the output of the second logic element AND, and the output is connected to the first input of the input trigger. Sources. Information taken into account in the examination 1. Copyright certificate of the USSR 552687, cl. H 03 K 5/13, 08.01.76, g / g.2