SU696599A1 - Pulse duration selector - Google Patents

Description

(54) SELECTOR OF PULSES OF DURATION

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Yeobretav is not related to the NMPU technology.

The selector of pulses is known for perfection, containing three input logic elements AND, waiting pulse generators, output transmission elements AND, the inputs of which are appropriately connected to the outputs of waiting generators and input logic elements And ij.

This selector does not provide sufficient selection accuracy.

The closest technical signal to the claimed is the pulse selector, which contains a differentiating element whose input is connected to an ACCELERATED SPINNER, and one output is connected to the first input of the logic element I, which are sequentially connected to a controlled clock generator: pulses, a counter and a decoder, the output of which is connected directly to the second input of the logical element AND, and through sequentially connected logical element OR and the delay element to the reset input of the counter 2.

This selector does not provide sufficient reliability.

The aim of the invention is to improve the reliability of selection.

The delivered ael is achieved by the fact that the pulse selector containing

differentiating element, the input of which is connected to the input bus, and one output is connected to the first input of the logic element AND, sequentially connected controlled oscillator

clock pulses, a pulse counter and a decoder, the output of which is connected directly to the input of the logical element I and through a series-connected logical element.

ment OR and delay element - with input, reset pulse counter, entered. trigger, one input of which is connected to the second output of the differentiating element, the second input is connected

with the output of the delay element, and the output is connected to the input of the controlled clock generator.

The structural electrical circuit of the selectable selector is shown in the drawing.

The write selector contains differentiating element 1, trigger 2, controlled clock pulse generator 3, counter 4, decoder 5, logic AND 6, logic OR 7, delay element 8, Selectable pulses are fed to the input bus 9, the output signal is removed from output 10.

The selector works as follows.

On the input bus 9 selector receives a pulse. From the first output of the differentiating element 1, the pulse of the leading edge of the estimated pulse is removed, from the second output the pulse of its trailing edge, which is fed to the first input of the logic element 6. The pulse of the leading edge of the selectable pulse arrives at the input of the trigger 2, which controls the operation of the clock pulse generator 3. The signal from the output of trigger 2 enters the clock pulse generator | which begins to generate clock pulses that arrive at the input of the counter. After the arrival of the p-th pulse from the output of the counter, the signal arrives at the input of the decoder, and an auxiliary impulse will be formed at its output - a pedestal, which is fed to the second input of the logic element AND 6. When the pulse-pedestal coincides with the trailing edge of the sec- lectured pulse at the output of the locking element. And a signal is generated.

The pulse of the falling edge of the selectable pulse is also fed to the input of the OR logic element and from the output of the delay element 8 the delayed signal (pulse of the falling edge) returns the selector to its initial state.

The protection against impulses, the duration of which is less than the time of selection, occurs due to the formed signal of resetting the back front of this impulse.

Claims (2)

1. Japanese Patent No. 3053, cl. 98 (15) 12, publ. O7.02.69. 2. USSR Author's Certificate No. 451186, cl. H 03 K B / 18, 04.14.72 (prototype).