SU1170601A2 - Pulse shaper - Google Patents

Abstract

FORMER PULSES by author. St. No. 911708, which is also distinguished by the fact that, in order to expand the functionality by reliably and reliably generating interdiction signals (rejection gate), a second counter, second comparator, trigger, second and third inverters, delay element, element are introduced into it AND-NOT and for the reset resetter, while the output of the first comparator through the second inverter is connected to the counter input of the counter, the output of the second bit of which is connected to the trigger input of the trigger, the inputs D and S of which are connected via a resistor to the positive to the source of the power source, and the trigger output is connected to the first input of the NAND element, the output of which through the reset shaper is connected to the R input of the trigger, the second input of the NAND element is connected via the second delay element to the i output of the second comparator, to the input of the third inverter whose output is SLF The Corno is connected to the R and 4 inputs of the counter, the first input of the second comparator is connected to the output of the first electric element, and the second input to the common terminal of the power source -.

Description

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The invention relates to a pulse technique and can be used in devices for detecting superimposed random triangular pulses, in particular, in an amplifier-conversion channel of x-ray spectrometers in order to form prohibition pulses (strobe) for their rejection.

The purpose of the invention is to expand the functionality of the pulse former by reliably and reliably generating inhibit pulses (rejection gate), to reject superimposed random triangular pulses in the measuring path of the spectrometer,

FIG. 1 is a functional diagram of a pulse former; FIG. 2 - time diagrams that show his work.

The pulse shaper contains an input bus 1 connected to the lane. the first input of the adder 2 and through the successively connected first delay element 3 and the first inverter 4 to the second input of the adder 2, the output of which is connected via a linear expander 5 to the first input of the first comparator 6, the second input of which is connected to the output of the first delay element 3, the second inverter 7, counter 8, trigger 9, resistor 10, NAND element 11, reset shaper 12, second comparator 13, third inverter 14, second delay element 15, with the output of the first comparator 6 connected via the second inverter 7 to the counter input of the counter The output of the second bit of which is connected to the synchronization input of the trigger 9, the inputs D and S of which through the resistor 10 are connected to the positive pole of the power supply + E,. And the output of the trigger 9 is connected to the first input of the element 11 AND-NOT whose output through the driver 12 reset is connected to the trigger input 9 a second input of the element 11 is NOT connected to the output of the second delay element 15, the input of which is connected to the output of the second comparator 13 and to the input of the third inverter 14 whose output is connected to the inputs R and & counter 8, the first input of the second comparator 13 is connected to the output of the first element 3 of the delay, and

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the second second comparator 13 is connected to a common power supply bus.

The pulse shaper operates as follows.

The superimposed triangular pulses (Fig. 2a), are delayed in the delay element 3 by the time t. from the output element 3 delay come

At the first input of the second comparator 13. The output of the second comparator 13 produces strobe pulses (FIG. 26), the duration of which is equal to the duration of the impulses generated by the low threshold of the second comparator 13, which through the third inverter 14 enters the inputs R and & counter 8 (Fig. 2B) and open it to account

Through the second inverter 7 logical pulses (Fig. 2-), the number of which is equal to the number of peaks of superimposed pulses (in this example, two pulses), arrive at the counting input of counter 8, which counts these logical pulses along their leading edge only during the strobe operation R and & and produces at the output of the second bit logical

a pulse (FIG. 22) of the counter 8 from the second logical pulse at the counting input of the counter 8. If the counting input of the counter 8 has only two pulses, then the logical pulse B of the counter 8 starts from the front

the front of the second logical pulse, and ends with the end of the inverted gate pulse.

The logical impulse of counter 8 is generated only if the number of superimposed, and consequently, logical impulses will be two or more (up to six), and comes from the output of the second bit

the counter 8 to the input C of the trigger 9, the inputs D and S of which through a resistor 10 are connected to the plus of the power source + E. The output Q of the trigger 9 produces a positive

the impulse (Fig. 2e) of the trigger, the leading edge of which coincides with the leading edge of the logical pulse of counter 8, and the leading edge is formed after resetting at the input R

trigger 9 and coincides with the falling edge of the gate of the rejection gate (Fig. 2), which is developed at the output of the logic element 11.

A strobe (Fig. 2) is outputted from the output of the second comparator 13 via a delay line 15 delayed by time t to the second input of the AND gate NI. Thus, the output of the logical element 11 AND-NOT produces a pulse (FIG. Strobe notch), the duration of which is equal to the duration of the gate (FIG. 2 &) delayed relative to the input signal by the total time t of the delay element (t) of the logic driver pulses and element 15 delays (tj) ..

tj t, + t., (1) A rejection strobe delayed by time t (1) (Fig. 2O is the output pulse of the proposed circuit and enters the key input of the measuring channel. A spectrometer measuring channel is inserted

delay line at time t, (1),

The reset shaper 12 generates a polo (effective pulse (Fig. 2qj units) after passing the back edge of the strobe pulse (Fig. 2a) and feeds it to the R input of the trigger 9, which places it in the initial state.

Thus, if a superimposed signal goes along the measuring channel, then the key of the measuring channel under the action of the gate of the notch (Fig. 2p is closed, thereby reducing the superimposed signals in the measuring channel.

The proposed pulse shaper produces a notch strobe in the event that two or more triangular pulses are applied at its entrance — and can be used to reject these pulses in the measuring channel.

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Claims (1)

SHAPE FORMER by ed. St. No. 911708, distinguishing with the fact that, in order to expand functionality by reliable and reliable generation of prohibition pulses (notch strobe), a second counter, a second comparator, a trigger, a second and third inverters, a delay element, an And element are introduced into it -NOT and reset driver, while the output of the first comparator through the second inverter is connected to the counter input of the counter, the second discharge of which is connected to the trigger synchronizing input, inputs B and 5 of which are connected through the resistor to the positive pole power source, and the output of flip-flop connected to the first input of AND-NO element whose output is through shaper relief connected to the input R flip-flop _f the second input of AND-NO element is connected via a second delay element to the output of the second comparator to the input of a third inverter whose output is connected to the inputs R and 4 of the counter, the first input of the second comparator is connected to the output of the first delay element, and the second input to the common bus of the power supply 1170601 2