SU898601A1 - Clock sysnchronization device - Google Patents

Description

one

The invention relates to a pulse technique and can be used to tie asynchronous signals to clock pulses.

A sync closure device is known that contains three triggers, five coincidence circuits and an inverter. The said device allows the asynchronous input signals to be linked to the clock pulses fl.

However, such a device is characterized by insufficient reproducibility with respect to short-term interference, since the effect of these interferences on the input of the device leads to a false response of the latter, as a result of which it generates an erroneous output signal.

The closest in essence to the invention is a clock synchronization device containing the first and second triggers, the AND-NOT element. The operation of this device is based on the principle of asynchronous coupling.

signals, nocTynafTJjix at its input, to clock (pulse.

A disadvantage of this device is the low noise immunity when exposed to short-term interference on its controls, an information input that can lead to a false formation of the output signals.

The purpose of the invention is to improve the noise immunity of the device.

The goal is achieved by the fact that the device of clock synchronization, containing the first and second triggers and the IS-NOT element, the first and second inputs of which are connected respectively to the clock input of the first trigger and to the single output of the second trigger, is inserted a third trigger, the zero output of which is connected to the third input of the NAND element, the output of which is connected to the clock input of the third trigger, the information and zero inputs of which are connected to the single output of the second trigger, information 389

oinibni and clock input of which are connected respectively to the single output of the first trigger and to the clock input of the first trigger.

The drawing shows a functional diagram of the proposed device.

The clock synchronization device contains the first trigger 1, the second trigger 2, the AND-NOT 3 element, the clock input 4, the information input 5, the output 6, and the third trigger 7.

Tact input 4 is connected to the first input of the element AND-NOT 3 and clock inputs of triggers 1 and 2. Information input 5 is connected to zero and information input of the first trigger 1, the unit output of which is connected to the information input of the second trigger 2. Single output of trigger 2 connected to the second input element AND-NOT 3, information and zero inputs of the third trigger 7, and the reverse output of which is connected to the third input of the element AND-NOT. The output of the element AND-NOT 3 is connected to output 6 and to the clock input of the third trigger 7.

The device works as follows.

The initial state of the triggers 1, 2 and 7 is zero. In the absence of an information signal at input 5, when a zero potential is present at this input, the clock pulses acting on input 4 confirm the zero state of the triggers 1 and 2. The zero potential at the single output of trigger 2 prohibits the passage of pulses through the IS-NE 3 and confirms the zero state of the trigger 7. A single potential, about 6pasyeNbift at the inverse output of the trigger 7, opens the AND-NE element 3 at the third input, i.e. prepares the passage of a clock pulse through the specified element to the output of the device. The device is ready to receive a synchronous signal.

When an asynchronous signal of positive polarity arrives at input 5, trigger 1 is prepared for operation. The clock pulse arriving after this, the leading edge throws Grigger 1 into one state, i.e. A single potential is established at its output. In this case, trigger 2 does not change its zero state, since at the moment

the onset of the action of this clock pulse at the output of the trigger 1 is still zero potential. The next clock pulse arrives at the clock inputs of triggers 1 and 2 before the front 1 flies trigger 2 into a single state. Trigger 1 remains in a single state, since its information and zero inputs are acted upon by a single potential (there is an asynchronous input signal present). On a single trigger output

2, the zero potential changes by one, which, acting on the second input of the AND-HE element 3, removes the prohibition of the clock pulse passing through it. As a result, a clock pulse passes through the element AND-NOT 3 to exit 6 of the SG-system. In addition, the potential at the output of trigger 2 enters the information and bullet inputs of trigger 7, as a result of which the latter is prepared for operation. The falling edge of the signal generated at the output of the NAND 3 element affects the clock input of the trigger 7 | Pey11 shoots it into one state. At the inverse output of the trigger 7, the unit potential changes to zero, which prohibits further passage through the NAND element

3 stroke signals. The device returns to its original state at. O1FORMS from the input 5 of a single potential, since after a reset to O of trigger 1, the next clock pulse overloads O to trigger 2, n, therefore, trigger 7.

When exposed to the information input 5 short-term interference occurs the following.

Claims (2)

If a pulse interference occurs before the clock pulse starts, and ends simultaneously with the clock pulse, or somewhat later than the clock pulse (before the next clock pulse begins), the first trigger 1 on the leading edge of the clock pulse switches to a single state. By the time of arrival of the next clock pulse, the noise at input 5 disappears, resulting in trigger 1 returning to zero (the initial; state, and therefore, the next clock pulse confirms the zero state of the trigger, hera 2. Therefore, the proposed device does not generate an output signal from interference. If a pulse interference arises before the onset of a clock pulse and partially falls into its zone (the interference ends before the clock pulse), then the first trigger 1 switch However, until the end of the current clock pulse, the specified trigger is reset to the zero state, since it disappears by this time. Consequently, in this case the device does not generate a false output signal, since it is reset to the initial state. of the next clock pulse. Thus, the proposed device, compared with the known one, suppresses short-term interference, the duration of which can reach up to one period of the following clock pulses. The invention is a clock clock device, containing first and second triggers and an IS-NOT element, the first and second inputs of which are connected respectively to the clock input of the first trigger and to a single output of the second trigger, in order to improve the noise immunity of the device, it is entered the third trigger, the zero output of which is connected to the third input of the element, AND-NOT, the output of which is connected to the clock input of the third trigger, the information and nupev L inputs of which are connected to the single u th trigger information and the clock inputs of which are respectively podyushcheny to a single output of the first flip-flop and to the clock vkodu first flip-flop. Sources of information, acceptance of P e in the introduction of the examination 1. The author's certificate of the USSR 1 4243, cl. H 03 K, 1972. 2. Authors certificate of the USSR, cl. H 03 K 5/13, 1975.