SU1019614A1 - Pulse-width selector - Google Patents

Abstract

SELECTOR YMYUYA OBG IN LONG TYPE,. containing impudas., first aHTOjt t perv: the second and the third (enta AND, the element OR, the inverter and, the Evolution for the operation, {video circuit b6ro- ii "rrepaqoe HHee: with the first vx6; o (ohm the first element | (i , and the single and zero VHO35Y - with the outputs of the second element AND and the element ISZH about; and with the fact that, with 1 noBtt of the current workability indicator, a pulse generator is inserted in it, the output of which is connected to. | vmv} sodo 1: the third element of AND,: to1 hey; the entrance to which is connected with its own bus (Devices and an input inver; b1 Eic6d with a count of values ka: pulsovk, Vkhod; reset kotbOyugo connected with) Iomonverto, iBTOpa of the first eltent I and zero input toTojporb: trigger, inverted, the output of which is connected to, first, 11, the second, the opposite inputs of the second; ni with sper; howl gryuyy razrydnYE of CleiTchik's exits (SOV - to the torus rpsSina which ral output exits are connected to G vsuadamk; "ivertrogo course p91DK CONC. through5 9l ““ bnt ad ck soy. inen with | ihrdnskhy1sh1noy device and, 1 output of the first element And, And f

Description

The invention relates to a pulse technique and can be used to extract pulse signals in automation devices. A pulse selector is known in duration, containing a trigger, two keys, a pulse counter, an AND element and a delay element, the output of which is connected via a successively connected trigger, keys and pulse counter, to the first input of the And element, and the control input of the first key, the second The input of the And element and the single input of the trigger are connected to the input of the delay element and the input bus, and the control input of the second key and the zero input of the trigger are connected to the output of the delay element and the third input of the electric amp and fl However, this device provides Pulse excitation with a duration shorter than that specified in the mask, and does not provide for the selection of pulses with a duration greater than a certain preassigned velocity. The closest in technical essence is a device into which, in comparison with the known, inverters are introduced, two additional elements AND, the first inputs of which are connected to the input bus, the second, inputs of the first directly, and the second through the first inverter. , and a third is the input of the first additional element AND to the output of the element: 3-delays, a trigger, the zero input of which is connected to the outputs of the additional elements AND through the OR element, and the single input to the output of the element whose fourth input is connected with the output of the first additional element And through the second inverter, and the output key, the control input of which is connected to the trigger output, and informational - to the output of the delay element 2. The disadvantage of this device is low reliability of operation, detectable possibility of false operation of the device when the duration of the input pulses exceeds the upper time threshold. The purpose of the invention is to increase the reliability of the device. The goal is achieved by the fact that the pulse selector has the pulse counter, the first and second triggers, the first, second, third and fourth; AND elements, the OR element, the inverter and the delay element, and the output of the first trigger is connected to The primary input of the first element is AND, and the single and zero input is with the outputs of the second AND element and the OR element, respectively, a Pulse generator is introduced, the output of which is. connected to the first input of the third element And, the second input of which is connected to the input bus of the device and the input of the inverter, and the output - to the counting input of the pulse counter, the reset input of which is connected to the output of the inverter, the second input of the first element I. and the zero-input of the second trigger, the inverse output of which is connected to the first input of the second element I, the remaining inputs of which are connected to the first group of discharge outputs of the pulse counter, the second group of discharge outputs of which are connected to the inputs of the fourth element And, output D of which is connected to the single input of the second trigger and the first input of the OR element, the second input of which is connected to the output bus of the device and the output of the first element I. Through the drawing, a block diagram of the pulse selector is given. The device contains a generator 1 {mpulsov, triggers 2 and 3, the elements of p 4-7, the element OR 8, the inverter 9, the counter 10 pulses, the element 11 of the delay, input and output bus 12 and 13. The device works as follows. in the initial position, the counter 10 and the triggers 2 and 3 are in the zero state. When the input pulse arrives at bus 12, element 6 opens and counter 10 starts counting the needle pulses of generator 1. The lower and upper thresholds are determined by multiplying the period of the pulse of generator 1 by the code corresponding to the number P1 sent to the counter input 10 ttulses fixed by elements 5 and 7, respectively i.e. elements 5 and 7 play the role of a code decoder on the corresponding group of bit outputs of counter 10. If the duration of the input pulse is greater than the lower threshold time, but less than the upper one, then element 5 triggers the trigger 2 to one, the first input of element 4 is received . level. At the moment of termination of the input pulse, element 6 closes, a unit level from the output of Inverter 9 sets the counter U to the initial connection and enters the second element 4, as a result of which bus 13 appears a pulse that transmits trigger 2 through elements 11 and 8 to zero state. The device is ready to analyze the next input pulse.

If the duration of the input pulse is less than the lower | threshold threshold, then element 5 does not work, and the device is reset to the initial edge of the input pulse.

If the duration of the input pulse is greater than the upper-time threshold, then during the time that it existed, trigger 2 would be successively switched to the single and zero state after the end of the pulse of pulse 4 on the bus 13 of the device. When switching trigger 2 to zero

The state of the host; translates into a single state of flip-flop 3, necessary to eliminate the ambiguity of the reference,. Trigger Translation

the zero state is performed by the level from the output of the inverter after the end of the input pulse.

Thus, the pulse selector is in duration, ensuring the selection of pulses within the specified limits, excluding false alarms if the duration of the input pulses exceeds the upper time threshold. Moreover, the duration of the output (7 pulses of the device is constant and is determined by the delay time of the delay element.

The introduction of a generator (spools. Does not lead to an increase in the cost of the device, since it allows the use of generators already existing in the receiving and processing units).

STREET SIGNS.

Claims (1)

PULSE SELECTOR BY LENGTH - comprising a pulse counter, first and second triggers, first, second, third and fourth elements and, an OR element, an inverter and a delay element, the output of the first trigger connected to the first input of the first element And, and the unit and zero inputs - with outputs of the second AND element, and the OR element, respectively, and so on, in order to increase the reliability of the operation, a pulse generator is introduced into it, the output of which is connected to the first input of the third AND element, the second input of which connected to input discharge bus _t unit and the input of the inverter, and an output - with a counting input of pulse counter / whose reset input is connected to inverter svyhodom, vtorm input of the first AND gate and nulevm input of the second flip-flop inverse output of which is connected to, pervm input of the second AND gates, the other inputs which are connected to the first group of discharge outputs of the pulse counter, the second group of discharge outputs of which is connected § to the inputs of the fourth element AND, whose output is / ffdc is connected to a single input. OR, the second input of which is connected through the delay element to the output bus of the device and · 2 .1 the output of the first element I. - JZ. From $ Ί