SU1293837A1 - Control device for forward-backward counter - Google Patents

Abstract

The invention relates to control devices for reversible counters of electrical pulses. It can be used in automatic control systems and in measuring devices. The device contains two pulse shapers, the item is NOT 12, the item is OR 11, the Pulse Shaper contains the triggers 7.9, the delay elements 8.10. To achieve this goal, the elements NOT 3,4 are inserted into the device, triggers 5,6, 1 Cp ff, 1 slug. (L N9 CO with OO 00

Description

I1

The invention relates to control devices for reversible counters of electrical pulses and can be used in automatic control systems and in measuring devices.

The aim of the invention is to increase reliability.

The goal is achieved by introducing new design features; to ensure that the input pulses are excluded from the processing of overlap.

The drawing shows a block diagram of a control unit for a reverse meter.

The device contains input shi1-sh 1 and 2, elements NOT 3 and 4, triggers 5 and 6, trigger 7, delay element 8, trigger 9, delay element 10, element OR 11, element 12, output tires to the bus 16 of a single potential.

Tires 1 and 2 are connected to clock inputs l and flip-flops 5 and 6, respectively, with the installation inputs to O flip-flops 6 and 5 and to the inputs of elements HE 3 and 4, whose outputs are connected to clock inputs of flip-flops 7 and 9si, respectively, whose information inputs are connected with the direct outputs of the flip-flops 5 and 6, respectively, the direct outputs of the flip-flops 7 and 9 are connected to the inputs of the delay elements 8 and 10, respectively, the outputs of which are connected to the inputs of the zero setting of the triggers 7 and 9, respectively, the direct outputs of which are connected to the first and the second inputs of the element OR 11 respectively, the output of which is connected to the output bus 13, the direct output of the trigger 9 is connected to the output bus 15 and connected through the element HE 12 to the output bus 14, the bus 16 of the single potential is connected to the information inputs of the trigger 5 and 6,

The trigger 7, the delay element 8 and the trigger 9, the delay element 10 constitute the pulse formers in duration.

Triggers 5, 6, 7 and 9 are triggered by the positive edge of the pulse arriving at the clock input and are asynchronously set to O with a single potential arriving at the installation input to

ABOUT

The device works as follows.

five

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In the initial state, the triggers 5, 6.7 and 9 were reset to zero. The reset of the trigger circuit is not shown in the drawing),

On bus 13, there is a zero signal; 1; on buses 14 and 15, there is a single and zero signal, respectively.

On the leading positive edge of the signal received via bus I, the trigger 5 is set. On the falling edge of the same signal, information from the output of the trigger 5 is written to the trigger 7.

The signal from the output of the trigger 7 through the element OR P enters the counting bus 13, while maintaining the same counting direction, i.e., a single signal on bus 14 and a zero signal on bus 15, After a time delay of the signal on element 8 on the output of the latter appears, the signal resetting the trigger 7 to the initial state, and the formation of the signal on the counting bus ends.

If during the time interval between the end of the current signal on bus 1 and the beginning of the next signal on the same bus, no signal arrived on bus 2, by the time the next signal arrives on bus 1, trigger 5 is in one state, and on the leading edge of the incoming signal the signal is confirmed by the state of trigger 5, the further operation of the device is similar to that described above,

If during the time interval between the end of the current signal on bus 1 and the beginning of the next signal on the same bus, bus 2 received a signal, by the time the next signal arrives, trigger 5 is in the initial state and the device operates as described above.

On the leading edge of the signal that has become scared along slit 2, the trigger 6 is set;

the front of the same signal information from the output of the trigger 6 is recorded in the trigger 9, the signal from the output of the trigger 9 is fed to the input element IL 1 1 and then to the bus 13 of the account. Wherein

after the installation of the trigger 9, a change in the counting direction occurs, i.e. A zero signal appears on bus 14, and a single signal appears on bus 15. Simultaneously, the signal from the output of trigger 9

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em to the input of the element 10 delay. After a time delay of the signal on the element 10, the trigger 9 is reset, and the formation of the signal on the counting bus 13 ends. The counting direction takes the original value.

Further operation of the device when the next signal arrives on bus 2 is carried out similarly to that observed when signals are received on bus 1,

If by the time the signal ends on bus 1 (bus 2) there is a signal on bus 2 (bus 1), then triggers 5 and 6 are reset, and on the falling edge of this signal, trigger 7 (trigger 9) confirms its initial zero state. In this case, the signal on the counting bus 3 is not formed and the counting direction does not change. Since by the time the signal ends on bus 2 (bus 1), triggers 5 and 6 are in the initial zero state, on the trailing edge of this signal, trigger 9 (trigger 7) also confirms its original zero state, the signal on the bus. the counting direction does not change.

Claims (2)

1. A reversible counter control device containing two input buses, an OR element, the first element is NOT, and the first, second formers are a pulse editor L. Povkhan Order 396/59 Compiled by Ranov Tehred V. Kadar Corrector Circulation 902 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab, 4/5 Production and printing company, Uzhgorod, Projecto st., 4 o five 0 five 0 owls, the outputs of which are connected respectively to the first and second inputs of the OR element, the output of which is connected to the first output bus, the second output bus is connected to the output of the first element NOT, the input of which is connected to the third output bus and the output of the second pulse shaper, that, with a reliability circuit, a single potential bus, two triggers and a second, third NOT elements, whose inputs are connected to the first and second input buses, are entered with the clock inputs of the first and second tr igger and with the inputs of the zero setting of the second and first triggers, the forward outputs of which are connected respectively to the resolution inputs of the second and first pulse formers, the clock inputs of which are connected respectively to the outputs of the third and second elements, the information inputs of the first and second triggers are connected to the single potential bus ,  2. The device according to claim 1, 1 and 2, which means that the pulse shaper contains a delay element and a trigger, the direct output of which is connected to the output of the pulse shaper and connected via the delayed element with the input of the zero setting) The information and clock inputs of which are connected respectively to the enable input and the clock input of the pulse generator. Proofreader M. Demchik