SU1324096A1 - Pulse train-to-square pulse converter - Google Patents

Abstract

The invention can be used in various radio devices, such as automatic control systems, as well as measurement technology. The aim of the invention is to extend the functionality for examining a series of pulses with previously unknown different intervals between pulses within one series. To achieve this goal, a device containing input 1 and 10 and output 14 buses, trigger 2, generator 4, pulse counter 5, comparison block 8 delay element 11 and element 15 also added pulse generator 3, the first 6 and the second 12 additional triggers, register 7, controlled divisor 9 and differential link 13. 1 slug.

Description

The invention relates to a pulse technique and can be used in various radio engineering devices, for example, in automatic control systems, as well as in measuring technique.

The purpose of the invention is to extend the functionality for the study of a series of pulses with different intervals between pulses s within one series that are unknown in advance.

The drawing shows a flow chart of a pulse train to a square pulse.

The pulse train to rectangular pulse contains the first input bus 1, trigger 2, shaper 3 pulses, pulse generator 4, pulse counter 5, first additional trigger 6j reg 7, comparison block 8, controlled divider 9, input bus lOj the delay element 11, the second additional Trigger 12, the differentiating element 13, the output bus 14, the element 15.

Input bus 1 is connected to the input of the pulse generator 3, the first output of which is connected to the single input of trigger 2, the recording input of register 7, the zero input of trigger 12 and the reset input of the divider 9, the control input of which is connected to the input terminal 10, the output is connected to the zero input of the trigger 2, and the summing input is connected to the output of the comparison unit 8, the zero input of the trigger 6 and the second reset input of the pulse counter 5, the first reset input of which

connected to a single input of the trigger 6 and the second output of the imaging unit 3, the third output of which is connected to one of the inputs of the element 15 And the other input of which is connected to the output of the generator 4 pulses, and the output is connected to the summing input of the counter 5 pulses and through the element 11 of the delay c unit input of the trigger 12, the output of which is connected to the gate input of the comparison unit 8, the first information input of which is connected to the code of the pulse counter 5 and the information input of the register 7, the output of which is connected to the second information the input of the unit 8 comparison, the control input of the register 7 is connected to the output of the trigger 6, and the reset input through the differentiating link 13 under

O

five

0 5

0

0

five

0

five

It is connected to trigger output 2 and output bus 14.

The Converter operates as follows.

In the initial position, when there are no pulses on the input bus 1, the trigger 2 is in the rumble state, in which the potential O is at its direct output. The zero potential will also be on the output bus 14, at the output of the differentiating link 13, at the first and second outputs of the driver 3, at the output of the delay element 11. The third output of the imaging unit 3 is in state 1. The outputs of counter 5, trigger 6, register 7, comparison block 8, controlled divider 9, trigger 12 are in an arbitrary state. ; With the arrival of pulses of the converted series from the input bus 1 to the input of the imaging unit 3, an inverted input signal is formed at its third output, and single pulses are formed at the first and second outputs, respectively, on the positive and negative edges of each pulse of the series being converted. The first impulse from the first output of the imaging unit 3 enters the single input of trigger 2 and sets at its forward output state 1 which arrives at the output bus 14 and at the input of the differentiating link 13, at the output of which a single impulse is generated that arrives at the input reset register 7 and sets at its output the status of O ... I

The impulse, coming from the first output of the formative 3 to the zero input of the trigger 12, sets at its output the zero state, which enters the gate input of the B block of comparison and prohibits its operation for the duration of the pulse coming from the input bus. The impulse from the first output of the former 3 is also fed to the reset input of the controlled divider 9 and sets it to the zero state. The impulse coming from the second output of the imaging unit 3 to the first input of the reset of the counter 5 and to the single input of the trigger 6 sets the state O at the output of the counter 5 and the direct output of the trigger 6, state 1.

At the end of the first pulse arriving from the input bus 1, the strobe signal from the third output of the former 3 is fed to the first input of the element 15 and allows the clock frequency to pass from the output of the generator 4 to the summing input 5 of the counter 5 and to the input of the delay element 11, from the output of which the pulses delayed relative to the input are fed to the single input of trigger 12 and set co-fO toxin at its output 1. Positive signal arrives from the output of trigger 12 to the building input of the comparison unit 8 and enables it to work. Thus, the installation of the trigger 12 with a delay of t5 relative to the clock frequency prohibits the operation of the comparison unit 8 during transients.

In the interval between pulses of the converted series, the counter 5 counts 20 clock pulses, the state code from the information output goes to the first information input of the comparison unit 8, the second information input of which receives 25 od register output 7, the comparison unit 8 compares the codes . In the interval between the first and second pulses, when the state of register 7 is zero, the comparison block 8 does not generate a comparison pulse at the output, since the comparison of the zero states of counter 5 and register 7 is prohibited by the rigger 12. The state of the controlled voltage does not change is.

With the arrival of the second pulse from the input bus 1, a single impulse is formed at the first output of the imaging unit 3, which enters the input of the register entry 7 and records the current state of the counter 5 to the register 0, also enters the zero input of the trigger 12 and inputs resetting the controlled divider 9 and setting them to the zero state. From the second output of the imaging unit 3, a single pulse arrives at the first input of the reset of counter 5 and to the single input of trigger 6 and sets them to condition O and 1, respectively.

50

At the end of the second pulse, the trigger 12 is set, the counter 5 and the comparison unit 8 resume their operation. If there is no comparison in the interval between pulses, then with the arrival of the next pulse of the series being converted into register 7, the new current is written

the state of counter 5, which is less than the previous one recorded in register 7

Thus, with the arrival of each next interval between pulses, the minimum value is stored in register 7, if a counter appears in the interval between pulses, which is equal to the register, then a comparison pulse is generated at the output of the comparison block 8, which is fed to the summing control input divider 9 and changes its state; it also goes to the second reset input of counter 5 and to the zero input of trigger 6 and sets state O on their direct outputs. Register 7 does not change. With the arrival of the next clock pulse, counter 5 resumes its operation. With the following equalities of the state of the counter 5 and the state of the register 7, 1 is added to the controlled divider 9, the counter 5 and the trigger 6 are zeroed. The code from the input bus 10 is fed to the control input of the controlled divider 9 and sets the permissible number of minimum intervals between pulses, after reaching which the output of the controlled divider 9 generates a pulse that arrives at the zero input of the trigger 2 and sets it to the forward output O.

If, in the interval between pulses, the state of the controlled divider 9, equal to the specified c, is not reached. the input bus 10, then with the arrival of the next pulse of the series being converted, the recording of the current state of the counter 5 into the register 7 is not performed, since the trigger 6 is set to the zero state. The device continues its operation until the trigger 2 is set to the zero state.

With the arrival of the next series of pulses from the first input bus, the operation of the converter resumes.

0 s

Claims (1)

50 claims A pulse train transducer into a rectangular pulse containing a pulse generator connected in series, an And element, a pulse counter, a comparison unit, as well as two input buses, a delay element and a trigger, the output of which is connected to an output bus differing from that. that, in order to expand its functionality, two additional triggers are introduced into it, a differentiating link, a register, a controlled divider and a pulse shaper, the input of which is connected to the first input bus, and the first one is connected to the single trigger input, the register entry, zero input the second additional trigger and the reset input of the controlled divider, the control input of which is connected to the second input bus, and the output is connected to the zero input of the trigger, the output of which through the differentiating link connected to the reset input of the register, whose information input is connected to the output of the pulse counter, the first input of which is connected to the single input of the first Auxiliary trigger and the second output of the pulse former, the third output of which is connected to another input of the I element, the output of which is connected through the delay element with a single input of the second additional trigger, the output of which is connected to the gate input of the comparison unit, another information input of which is connected to the register output, and the output connected to the summing input of the controlled divider, the second reset input pulse counter and zero input of the first additional trigger, the output of which is connected to the control input of the register.