SU1647877A1 - Device for tolerance testing of time intervals between pulses - Google Patents

Abstract

The invention relates to a pulse technique and can be used to control the time intervals between pulses. The tolerance control device for the time intervals between pulses contains the back edge shaper 1 Pulse input, triggers 2 and 7, 3 clock pulses generator, 4 pulse counter, shaper 5 shaper driver, And 6 element, input bus 8, output bus 9. Exclusion spurious pulse on the output bus in the case of pulses on the input bus leading in time to the gate and overlapping with it, as well as in the case that the interval t between the input pulses is in the interval (K + tH) t (K Tssch + tH + At), where Tsh is the time of maximum filling of the pulse counter; tH - lower limit of tolerance control; At is the value of the control gate; To 1. allows to increase the reliability of the control. 1 hp f-ly. 2 Il. . w ё

Description

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The invention relates to a pulse technique and can be used to control the time intervals between pulses.

The purpose of the invention is to increase the reliability of monitoring by eliminating the possibility of a false pulse on the output bus in case of pulses arriving at the input bus, which are ahead of the gate and overlapping with it, and also if the interval between the input pulses t is in the interval ( To TSch + tn). t (К -104 + 111 + + At), where TSH is the time of maximum filling of the pulse counter, in is the lower limit of the control tolerance, At is the value of the control gate, K 1.

FIG. Figure 1 shows the electrical structure of the device; Fig. 2 shows timing diagrams explaining the operation of the device.

The device contains a back edge-forming driver 1, the output of which is connected to the R input of the first trigger 2. The output of the controlled generator 3 clock pulses is connected to the counting input of the counter of 4 pulses, the outputs of which are bitwise connected to the inputs of the forming device 5 of the control gate, whose output is connected to the second input element And b and D-input of the second trigger 7, the C-input of which is connected to the input bus 8, the input of the driver 1 and the first input of the element And 6. The output of the trigger 2 is connected to the output bus 9, and the S-input to the output of the element AND 6. The overflow output of the counter 4 is connected to the R input of the trigger 7, the output of which is connected to the control input of the generator 3, and the S input to the output of the driver 1 and the reset input of the counter 4,

FIG. 2 numerical designations of time diagrams correspond to the numbers of elements and tires. .

The device works as follows.

The device is reset to its original state by a pulse that is formed from a slice. input pulse shaper 1 and enters the S-input of the trigger 7, set it to the state of logic 1. In addition, this pulse is fed to the reset input of the counter 4 and R-bypass trigger 2, set them to the state of the logical O. At the address inputs the storage unit on which the driver 5 is made, sets the address of the zero memory location, and at its output the information recorded in this location. At the output of the trigger 2, a low voltage level is set. The signal from the output of the trigger 7 is fed to the control input of the generator 3, which begins to issue clock pulses to the counting input of the counter 4.

In the process of counting the counter 4 clock

the pulses are sequentially polled the contents of the memory cells of the storage unit in the imaging unit 5. In its first h cells, determining the time of the beginning of the monitored time interval (so-called) according to the formula tn n Tp, where Tn is the period of the clock pulse, zero information is recorded. In the next m cells of the memory block of the imaging unit 5, defining the tolerance control interval, a single information is recorded. The interval value (t0-tH) is determined by the formula () m Tn, where to is the interval end time. AT

the remaining stack of the memory unit of the memory generator 5 is recorded with zero information. Thus, the flow of the required time interval at the output of the storage unit of the imaging unit 5

forms a strobe of positive polarity, which is fed to the second input of the element AND 6, as well as to the D input of the trigger 7.

The input pulse is fed to the C input of the trigger 7 and the first input of the element And 6.

If the input pulse arrives at time tnx, which is within the interval specified by the start time tr and the end time to, i.e. tH tB to, then it passes through the element 1/1 b, since on its

the second input comes a strobe from the output of the driver 5. The pulse from the output of the element Ib goes to the S input of the trigger 2. The trigger 2 is set to the logical 1 state, from its output a positive polarity is output to the output bus 9 of the device. The front of the input pulse, arriving at the C input of the trigger 7, maintains it in the logical 1 state, since at this time the D input of the trigger 7 arrives

the strobe from the output of the driver 5. At the moment of termination of the input pulse, the driver 1 generates a pulse that also supports trigger 7 in the state of logic 1. In addition, the pulse from the output of driver 1 zeroed counter 4 and trigger 2. At the output of trigger 2, m. e. on the output bus 9 of the device, a low voltage level is set. Counter 4 starts counting the pulses of the new formation cycle.

the required time interval and the control of the presence of the next input pulse in it.

Thus, when an input pulse hits a predetermined time interval, it is output without distortion to the output bus 9 of the device.

If the input pulse arrives ahead of the start time of the tax tH interval, then with its front it sets trigger 7 to the logical state O, since the gate at the output of driver 5 has not yet begun to form and a low voltage level is present at the D input of trigger 7. The clock flow to the counting input of counter 4 is stopped. The pulse does not pass through the element And 6 to the S-input of the trigger 2 also due to the absence of a gate at the second input of the element And b. Trigger 2 remains in the logical O state; no pulse is generated on bus 9. After a cut-off of the input pulse, the device is reset, after which a new cycle of forming the desired time interval begins.

 Similarly, when the input pulse arrives after the end of the specified time interval tex t0, but before counter 4 overflows, the trigger 7 by the front of the input pulse is set to logical O, since the strobe formation has already ended and a low voltage level is set at the D input of the trigger 7 . Counter 4 stops counting. The input pulse through the element 6 does not pass, the trigger 2 remains in the state of logical 0, the pulse on the bus 9 is not formed. If the input pulse does not arrive at the moment when the counter 4 overflows, then the pulse generated by the overflow at the transfer output 4 arrives at the R input of the trigger 7 and sets it to the logical state O. The arrival of the clock pulses at the count input of the counter 4 stops. The input pulse through the element And b does not pass, the trigger 2 remains in the state of logical O, the pulse on the bus 9 is not formed. At the cut-off point of the first incoming pulse after this, a new cycle begins.

formation of the required time interval.

Claims (2)

1. The device tolerance control time intervals between pulses containing the element And, the first input of which is connected to the input bus and the input of the back edge of the pulse generator, and the output - with the S-input of the first trigger, the output of which is connected to the output bus, and the R-input - with the output of the back of the front pulse generator and the reset input of the counter pulses, the counting input of which is connected to the output of the clock pulse generator, and the outputs are parallel with the inputs of the control gate generator, the output of which is connected to the second input of the element I, which is so that, in order to increase the reliability of control by eliminating the possibility of the appearance of a false pulse on the output bus in the case of the arrival on the input bus of pulses that are ahead of the time of the control gate and overlap with it, and also if the interval between input pulses t is in the interval (K Tcc + tH) t (K Tcch + Tn + + At), where Tcch is the time of maximum filling of the pulse counter; t (l - lower limit of control tolerance; At - tolerance control; 1, a second trigger has been entered into it, the S input of which is connected to the output of the rear edge generator of the pulses, the C input with the input bus, the O input with the output of the control gate generator, R the input with the pulse counter overflow output, and the output with a control input of a clock pulse generator, made controllable. 2. Device pop. 1, characterized by the fact that the control gate driver made in the form of a storage unit, the address inputs of which are bitwise connected to the inputs of the control strobe generator, and the output - with the output of the control strobe body.