SU1251302A1 - Device for generating pulse sequences - Google Patents

Abstract

The invention relates to a pulse technique, can be used in automation devices and computing devices. The aim of the invention is to increase reliability. Into a device containing a clock pulse generator 1, elements AND 2, 3, 11, counters 4, 5 pulses, block 6 elements AND, delay element 7, trigger 8, input 12 and output 9, 10 buses, the inverter 13 is entered to achieve the target. The second element is 14 delay. The pulse period T on the output tires 9 and 10 of the device will be equal to T Ki / Ft + + K2 / Pt, while the value of Ki / Ft is constant, and K2 / Fi may vary depending on the pulse duration on the input bus 12 of the device (Ki , Кз - coefficients of recalculation of the counter 5 pulses; FT - frequency of the generator 1). If it is necessary to increase only the division factor Ki, increase the pulse width of the pulse counter 5 (without increasing the pulse width of the pulse counter 4). 1 il. a & (L CL to ate about to

Description

The invention relates to a pulse technique and can be used in automation and computing devices.

The purpose of the invention is to increase the 1: with reliability.

In the drawing, the representation of the uncnion fnn:;. Is a diagram of a device for generating n: i i pulse sequences.

The device contains i-generator 1 clock pulses, elements And 2, 3, counters 4 and 5 pulses, block 6 elements And, element 7 delay, trip-er 8, output bus 9 and 10 devices, element 11, input bus 12, an inverter 13 and a delay element 14.

In the device, the output of the generator 1 clock pulses is connected to the first inputs of the elements 2, 3, whose outputs are connected to the counting inputs of counters 4 and 5 pulses, the outputs of the counter 4 Izhpulsov through the first inputs of the block 6 elements I connection to the information inputs of the second counter 5 emuls. set.- the new output of which is connected to the input of the delay element 7. The first output of the trigger 8 is the output 1 of the 9 device, and the second is the output bus 10 of the device, which is connected to the first input of the element AND 1 1. The input LiiHiia 12 of the device is connected to the second input of the AND element 2 and through the inverter 13 to the second input of the element 3. The output of the delay element 7 is connected to the second input of the element I, the output of which is connected to the second inputs of the block 6 of the elements I. The output BTOpoi o of the pulse counter 5 is connected to the counting input of the trigger 8 and each of the back-load element 14 by its installable input.

The device works as follows.

In the initial state, the counters 4 and 5 pulses are volled. When the device of a single pulse of the reference duration is input to the input P1INS 12, the clock pulses from the clock generator 1 arrive through the open element I 2 to the counting input of the counter 4 pulses and start it.; 1nb. At this time, the element And 3 closed iu the left signal from the output of the inverter 13.

By the moment the pulse ends at the input P1ine 12, the state of the bits of the counter 4 pulses will be determined unambiguously 1, by the military expression of the number of pulses recorded in the counter 4 pulses during the pulse operation on the input bus 12.

With the end of the pulse on Hjnne 12, the And 2 element is closed, and the And 3 element is opened by a single, pure signal from the output of the inverter 13.

Clock emulsions from the output 1 of the generator;) - the clock clock pulses through the element And 3 arrive at the counting input of the counter 5 im-, i, ibcoB, the coefficient of which recalculation is equal to K |. When the pulse counter 5 is filled, a pulse is formed at its output.

The duration of this pulse is determined by the parameters of the delay element 14 and is selected taking into account the requirements for the duration of the pulses sent to the installation and information inputs of the pulse counter 5. By this pulse, the trigger 8 is transferred to the one state. A pulse from the output of the delay element 14 zeroes the pulse counter 5 and starts the delay element 7. The magnitude of the delay of the delay element 7 should not be less than the magnitude of the delay of the delay element 14, so that the ICFOR: 1a 1, IS (pulse inputs of the pulse counter 5), the pulse arrived after the impulse ended; 1VS at the installation input of the pulse counter 5 .

The unit potential from the output of the trigger 1 8 element And 1 is open. The delayed pulse from the output of the delay element 7 through the second input element And 11 enters the second inputs of the block 6 elements And, on the first inputs of which there is an inverse, | 1. counter code 4 and. “pulses, and rewrites this code into the pulse counter 5, thereby changing its recalculation coefficient, which will now be equal to K2.

Clock pulses 1 pulses start to flow to the counting input of the counter 5 pulses, fill it.

The beginning of the formation of the output pulse on the output buses 9 and 10 will be determined by the appearance of a pulse at the output of the pulse counter 5 after the time Ti: Ki / Fi, and through the pulse T2 the end of the output pulse will be formed, where FI is the generator frequency.

In the future, the device operation cycles will be repeated, and the pulse period on the output tires 9 and the device JO will be equal to .1

Ki

TO

n p and

Iirl

It

In this case, KI / FT is constant, and K2 / F-t may vary in heading. YES of the pulse duration on the inlet bus 12 determines the need to increase only the coefficient.; - ;, dividing Ki increases the counter size of impulses (without increasing the counter number of 4 pulses). At the same time, the information inputs of the additional spacer} of the first bits of the counter 5 are imp. 1c is connected to the output of the elementand And 11 (not shown).

A device for generating pulse sequences containing a clock pulse generator, the output of which is connected to the first inputs of the first and second elements AND, whose outputs are connected respectively to the counting inputs of the first and second counters and pulses, the outputs of the first counter of pulses through the first the inputs of the block e. And connected

1251302.

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with the information inputs of the second counting element of the delay and the inverter, the pulse input, the output of which is connected to the input bus by the device, the input of the first delay element, the first, and the output connected to the second input; the second output of the trigger is connected to the first output of the third element And, the second input of the third device bus, and the second output of the sub-element I is connected via the second elec- trine to the second output bus the device- 5 delay to the installation input of the second and the first input of the third element And the ry pulse counter the device input bus is directly connected to the second and through the first delay element to the counting input of the first element I, which distinguishes the trigger input, the output of the third one, in order to increase the AND output connected to the second inputs of the reliability unit device, it entered the second elements I.

Claims (1)

Claim A device for generating pulse sequences containing a clock pulse generator, the output of which is connected to the first inputs of the first and second pulse meters, the outputs of which are respectively connected to the counting inputs of the first and second pulse counters, the outputs of the first pulse counter through the first inputs of the block of elements And are connected to information inputs the second pulse counter, the output of which is connected to the input of the first delay element, the first trigger output is connected to the first output bus of the device, and W Ora output is connected to the second output line ⁵ ustroyst- va and the first input of the third AND gate, the input bus device connected to the second input of the first AND element, characterized in that, in order to increase the device reliability, it entered Auto swarm delay element and inverter, whose input is connected to the input bus of the device, and the output is connected to the second input of the second element And, the second input of the third element And is connected through the second delay element to the installation input of the second pulse counter directly and through the first element nt delay to the count input of the flip-flop, the output of the third AND element is connected to the second inputs of block elements I.