SU1365044A1 - Device for measuring momentary rate of time piece - Google Patents

Abstract

Invention m. used in the time industry. The purpose of the invention is to simplify the device. In the case when the monitored clock is in a hurry, the counter with the decoder 3 starts to work, at the second output of which a pulse is formed, which arrives at the pre-installation input of the measuring unit 6. The 14 pulse corresponding to the max. put the value of the instantaneous movement of the clock. Then a pulse is formed at the first output of the counter with the decoder 3, the trigger 5 is set to 1, the trigger 4 is set to O. At the output of the element I 13 there appear pulses arriving at the counting input of the measuring unit 6 from the bus 1. The counter 14 operates in subtraction mode. The counter with decoder 3 stops working. Upon receipt of the next pulse of the clock, the counter with the decoder 3 is resolved and the counter 14 stops, the contents of which is the result of the measurement in the cycle between the first two clocks of the clock, which goes on the display. The case when controlled hours are lagging behind, 3 Il. o (l

Description

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The invention relates to the field of instrumentation and can be used in the watch industry to measure the instantaneous movement of hours.

The aim of the invention is to simplify the device.

Fig, 1 shows a functional diagram of the device; g, 2, and 3 are the time diagrams that give descriptions of the operation of the device, respectively, when the controlled hours are ahead or lagging.

The device (FIG. 1) contains a clock bus 1, a bus clock signal bus 2, a counter with a decoder 3, a first trigger 4, a second trigger 5, a measuring unit 6, an overflow signal driver 7, a third trigger 8, a data bus 9, a bus 10 overflow signal bus 11.

The counting input of the counter with the decoder 3 is connected to the counting input of the measuring unit 6 and the bus 1 clock pulses, the input of the installation of the triggered 4 is connected to the bus 2 signals of the clock, the second reset input of the trigger 5, the reset input of the counter with the decoder 3 and the fourth input of the racer 7 overflow signal. A single trigger output 4 is connected to a counter enable input with a decoder 3 and a fifth input of the overflow signal generator 7. The first output of the counter with the decoder 3 is connected to the installation input of the trigger 5, the reset input of the trigger 4 and the reset input of the trigger 8, the output of the counter with the decoder 3 is connected to the installation input of the measuring unit 6, the unit output of the trigger 5 is connected to the resolution input of the measuring unit 6 Inverse output the trigger 5 is connected to the third input of the overflow signal generator 7, the output of which is connected to the trigger setup input 8. The information output of the measuring unit 6 is connected to the information bus 9, the sign bit output a measuring unit 6 connected to the bus plate 10 and the second input of the overflow signal 7, a first input coupled to an output of the overflow measuring unit 6. The output trigger 8 is connected to a first reset input of flip-flop 5 and the overflow signal bus 11.

Measuring unit 6 contains And 12 and 13 elements, reversible decimal counter 14, 15-character trigger. The first inputs of And 12 and 13 elements are combined and are the counting input of measuring unit 6, the second inputs of And 12 and 13 elements are also combined and are the input of the permission account

The measuring unit 6, the outputs of the elements And 12 and 13 are connected respectively to the clock inputs of the forward and reverse counting of the reversible decimal counter 14, the parallel recording input of which is combined with the reset input of the trigger 15 of the sign and is the input of the presetting of the measuring unit 6 (information the inputs of the parallel input of information into the counter 14 are not shown). The outputs of the bits of the counter 14 are the information outputs of the measuring unit 6, the Output P (transfer signal for direct count) is the output

The house of the Overflow signal of the measuring unit 6, Output 0 (transfer signal for down counting) is connected to the installation input of the trigger 15 characters. Single and inverse outputs trigger

Par 15 is connected to the third inputs of the elements 12 and 13, respectively. The unit output of the character trigger 15 is the sign bit output of the measuring unit 6.

The overflow signal generator contains an AND-OR-NOT 16 element and implements the following logical relationship:

40

F 1-2 + 2 3-4 -5,

where F is the designation of the function of the output signal of the imager 7; 1,2,3,4 and 5 - designation of inputs

shaper.

45 In FIG. 1, as an example of the technical implementation of a driver 7, an AND-OR-NOT element is shown with the number of inputs defined by the specified logical ratio. 50 The device operates as follows.

In the initial state, the counter with the decoder 3, the triggers 4.5 and 8, as well as the reversible decimal counter 55 14 and the trigger 15 of the measuring unit 6 are in the zero state. On the bus 1 clock pulses there are pulses of the reference frequency from the crystal oscillator (not shown).

There are no signals on the bus 2 of the clock run signals, on the information bus 9, the 10-character bus and the overflow signal bus 14 there are logical zero potentials.

The measurement cycle of the instantaneous stroke starts when the signal for the clock travels on the bus 2 as a predetermined

trigger 4 zero (FIG,

returns to the state 2d) and at the same time the reset (confirms the zero state) of the trigger 8 is effected. As a result, the potential of the logical unit arrives at the input of the account resolution of the measuring unit 6 from the single output of the trigger 5

radially formed right-angle cops And 12 and 13. At the output of the element

It has a pulse with a duration less than the period of the following clock pulses on bus 1. On the leading edge of this pulse, the counter with depressor 3 is zeroed (the zero state is confirmed), and on the falling edge trigger 4 is set to the state one and the zero state of the trigger 5 is confirmed. Since the trigger 4 is set to a single state on the trailing edge of the pulse, the potential of a logic zero at its single output before triggering the trigger 4 prohibits the passage of a clock pulse to the output of the 7 ovatel overflow signal. After triggering the trigger 4, the potential of a logical unit at its output resolves the counting by the counter with the decoder of 3 clock pulses received via bus 1.

Consider the operation of the device for two cases: the first, when the controlled clock is in a hurry, and the second, when the controlled clock is lagging.

In the first case, after the arrival of the pulse of the clock on the bus 2 (Fig. 2b), on the trailing edge of this Htr pulse, trigger 4 is set to

And 13 pulses appear (Fig. 2e) arriving at the counting input of the measuring unit 6 from the bus 1. The counter 14 operates in the subtraction mode. The counting

15 tick with decoder 3 stopped working, because at its input the resolution of the account with a single output of trigger 4 receives the potential of a logical zero. When entering through bus 2, the following

On the 20th pulse of the clock (Fig. 2a), on the leading edge of this pulse, the counter is cleared with the decoder 3, and on the falling edge, the trigger 4 is set to

25 units (FIG. 2 d), and trigger 5 to the zero state (FIG. 2 e). In this case, the operation of the counter with the decoder 3 is again permitted, and the potential of the logical zero from the single output

The 30 trigger 5 closes the AND 12 and 13 elements, as a result of which the counter 14 stops working. The contents of the counter 14, which is the measurement result from the cycle between the first two clock pulses, goes to the information outputs of the measuring unit 6, and consequently, to informational fault 9, from where it goes to the display (indication block

single state (Figure 2d). Beginning- 40 not shown). At the same time, the counter with the decoder 3 is operated, at the second output of which a pulse is formed (Fig. 2b), which enters the input of the presetting of the measuring unit 6. This HNT pulse records the 14th number corresponding to the maximum positive value (the measurement limit) instantaneous running of the clock (for example, 99, 99 with a four-decade counter 14), and the trigger 15 of the sign is set to the state corresponding to the positive sign of the measurement result (the state of logical zero). Then, a pulse is formed at the first output of the counter with decoder 3 (Fig. 2c), on the leading edge of which the trigger 5 is set to the state of one (Fig. 2e).

To it, the front of the second pulse of the clock begins a new measurement cycle.

In case when the signal of the clock

45 will arrive until a pulse appears at the first output of the counter with decoder 3, the pulse from the second output of the counter with decoder 3 (Fig. 26) is written to counter 14

50 is the number corresponding to the measurement limit, and the sign trigger is set to the position corresponding to the positive sign of the measurement result. Incoming pulse of the clock

55 passes to the output of the overflow signal generator 7, since at its second, third and fifth inputs there are potentials that allow the passage of the pulse of the clock,

And 13 pulses appear (Fig. 2e) arriving at the counting input of the measuring unit 6 from the bus 1. The counter 14 operates in the subtraction mode. The counting

A decoder with a decoder 3 has stopped working, because at its input the account resolution from a single output of trigger 4 receives the potential of a logical zero. When entering through bus 2, the following

on the leading edge of this pulse, the counter is reset with the decoder 3, and on the trailing edge the trigger 4 is set to

units (FIG. 2d), and trigger 5 to the zero state (FIG. 2d). In this case, the operation of the counter with the decoder 3 is again permitted, and the potential of the logical zero from the single output

trigger 5 closes elements 12 and 13, as a result of which counter 14 stops working. The contents of counter 14, which is the measurement result from the cycle in the cycle between the first two clock pulses, goes to the information outputs of the measuring unit 6, and therefore to the information window 9, from where it comes to the display (display unit

not shown). At the same time, a new measurement cycle begins on the trailing edge of the second pulse of the clock.

In the case where the signal of the clock

will arrive until the pulse appears at the first output of the counter with decoder 3, the impulse from the second output of the counter with decoder 3 (Fig. 26) to counter 14 is written

the number corresponding to the measurement limit, and the sign trigger is set to the position corresponding to the positive sign of the measurement result. Incoming pulse of the clock

passes the output of the overflow signal generator 7, since at its second, third and fifth inputs there are potentials that allow the passage of the pulse of the clock,

stupid on the fourth entrance. On the falling edge of the pulse at the output of the overflow signal generator 7 (FIG. 2l), the trigger 8 (Fig. 2m) is triggered, as a result of which the logical unit signal arrives on the overflow signal bus 11. At the information bus 9 at this time there is information corresponding to the limit of measurement (for example, 99.99 s / day), on the bus 10 characters there is a potential corresponding to a positive sign of the result. Block indication

In this case, it displays information- ig on bus 1 to the output of the element And 13

about the sign of the result and overflow in the measurement. At the same time, on the leading edge of the clock pulse, the counter is reset with the decoder 3, and on the rising edge the unit state of trigger 4 (FIG. 2d) is confirmed, then the device operation cycle repeats. Fig. 2 also shows the signal at the output P of the counter 14 (Fig. 2i), the incoming 25 state corresponding to the first input of the overflow signal 7 that is denied to the first input, and (dotted line) the expected position of the pulse at the output 0 of the counter 14 (Fig. 2c). ). Immediate measurement result (Fig. 3k). This closes the element And 13 (fig.Ze) and opens the element And 12, the output of which

35

pulse At the output P of the counter 14, the clock pulses do not appear (Fig.Zh).

The counter 14 goes to the summation mode. When the next pulse of the clock arrives (fig.Za), its leading edge resets the counter from the decoder 3, and on the falling edge, trigger 4 is set to unit state (fig.G), trigger 5 is set to zero (4ig. ). Potential logical unit with

The 40 outputs of the trigger 4 enable operation of the counter with the decoder 3. The potential of the logical zero from the output of the trigger 5 closes the elements 12 and 13. The counter 14 stores the measurement result,

45 which enters information bus 9 for indication. There is a potential on the tire 10 of the sign, which corresponds to a negative measurement result. Further, the cycle of

gQ you repeat.

In the event that the clock travel signal arrives at a time that exceeds the filling time of counter 14 to the maximum value, the output of the overflow P of counter 14 causes a pulse (Fig. 3i), which due to the potential of the logical unit at the second input of the imaging unit 7 the overflow signal will go to its output

This affects the operation of the device, since it is blocked by the potential of a logical zero coming from the output of the sign bit of the measuring unit 6 to the second input of the overflow signal generator 7.

The time interval between the pulse of the clock and the pulse at the output 0 of the counter 14 is equal to the measurement time (for example, 2 s). Based on the measurement time and the required resolution, the frequency of clock pulses on bus 1 is selected (for a resolution of 0.01 s / day, the frequency of clock pulses should be equal to 4.32 MHz.)

In the second case, when the monitored clock is lagging, the pulse of the clock (Fig. 3a) arriving via bus 2 zeroes the counter with decoder 3 and the trailing edge sets trigger 4 to one, and trigger 5 to zero. The counter begins to work with the decoder 3, on the second (FIG. 3b), and then on the first (FIG. 3c) outputs of which pulses are formed. The pulse at the second output of the counter with decoder 3 is written to the account 55

Figure 14 is the number corresponding to the selected limit value and sets trigger 15 to the state corresponding to the positive sign of the measurement result. But the leading edge of the pulse at the first output of the counter with the decoder 3, the trigger 5 is set to one (FIG. 10), and the triggers 4 (FIG. 3g) and 8 to the zero state. The potential of the logical unit from the unit output of the trigger 5 permits the passage of clock pulses arriving

(Fig. Ze), as a result of which the reversible decimal counter 14 starts to operate in the subtraction mode. Clock pulses are present at the output of the element And 13 until the appearance of a pulse at the output O, i.e. until the moment when the counter is set to zero. On the falling edge of this pulse, trigger 15 is set to

the measurement result (Fig. 3k). This closes the element And 13 (fig.Ze) and opens the element And 12, the output of which

(fig, 3l). On the falling edge of this pulse, the trigger 8 is set to one state, as a result, the trigger 5 returns to the zero state (Fig. 3b), and the potential 1 logic potential is present on the overflow signal bus 11, indicating an overflow when measuring the device's discharge grid. The display unit at the same time displays information about the sign of the result and the overflow of the discharge grid during measurement. Upon receipt of the next pulse of the clock, the cycle of operation of the device is repeated. In the absence of a clock signal on bus 2, the output of the device stores the result of the last measurement.

Claims (1)

Invention Formula An apparatus for measuring the instantaneous movement of a clock, comprising a counter the output of the first trigger is connected to the counter enable input with a decoder, the first output of which is connected to the installation input of the second trigger, and the output of the third trigger is connected to the overflow signal bus, characterized in that, in order to simplify the device, 10, an overflow signal generator is inserted into it, and its output is connected to the installation input of the third trigger, the output of which is connected to the first reset input of the second trigger 15 ger connected by its direct output to the resolution input of the measuring unit, the clock signal bus is connected to the installation input of the first trigger, the reset input of the counter with 20 decoder, the second reset input of the second trigger and the fourth input of the overflow signal generator, the first input of which is connected to the overflow output of the measuring unit with the decoder, three triggers, a measuring unit 25, connected to the input of the mounting unit, information bus, new to the second exit counter with clock bus, signal bus decoder, and the reset inputs of the first catching the course of the clock, the tire of the sign and the tire of the third trigger are connected to overflow signals, with the gate input of the second trigger, clock pulses connected to the counting; the inverse output of which is connected with the inputs of the counter with the decoder and the measuring unit, the information output and the output of the sign bit of which are connected respectively to the information bus and the sign bus. the output of the first trigger is connected to the counter enable input with a decoder, the first output of which is connected to the installation input of the second trigger, and the output of the third trigger is connected to the overflow signal bus, characterized in that, in order to simplify the device, 0, an overflow signal generator is entered into it, and its output is connected to the installation input of the third trigger, the output of which is connected to the first reset input of the second trigger 5 ger connected by its direct output to the resolution input of the measuring unit, the clock signal bus is connected to the installation input of the first trigger, the reset input of the counter with 0 by the decoder, the second reset input of the second trigger and the fourth input of the overflow signal generator, the first input of which is connected to the output of the third input of the overflow circuit connected with its second and fifth inputs respectively to the sign bus and the output of the first trigger. v ABOUT c ")