SU1275314A2 - Digital frequency meter - Google Patents

Abstract

The invention relates to the field of digital measurement technology, can be used for accurate and accelerated measurement of low and infra-low frequency signals with the presentation of measurement results in units of frequency, and is an additional invention to the model number 1190285. The purpose of the invention is to simplify the device. containing the source 1 of the model period, elements And 2, 3 and 13, triggers 4 and 14, counter 5 with decades, oo “,, shaper 6 time intervals consisting of the decoder 7 code, element OR 8; drivers 10 and 12, bus: input P, start 15, shift register 16, code multiplier 17, valve group 18, display device 19, unit 9 for forming the first measuring interval are made in the form of series-connected elements. AND 20 and trigger 21. Technical the advantages of the device are concluded (L in reducing the meter, increasing its technological efficiency, with cost reduction with constant accuracy characteristics. 1 ill. N)

Description

The invention relates to digital measurement technology, can be used for accurate and accelerated measurement of low and low frequency signals with the presentation of measurement results in units of frequency and is an improvement of the invention according to the authors. St. № 1190285о

The aim of the invention is to simplify the device due to the simpler implementation of the block forming the first measurement interval.

The drawing shows a functional diagram of a digital frequency meter. The digital frequency meter contains the source 1 of the model period T, the first 2 and the second 3 elements And, the first trigger 4, the counter 5 with serially connected decades; 5-1, 5-2, oo. , 5-k, shaper 6 time intervalsWD In the composition of which the code decoder 7, the element OR 8 and the block 9 forming the first measurement interval, the first shaper 10 connected to the bus 11, the second shaper 12 short pulses, the third element And 13, the second trigger 14, run tires 15, shift register 16, multiplier 17 code, valve group 18, display device 19. Block 9, in addition, contained an element 20 and a trigger 21. In a digital frequency meter, the output of the source 1 of the reference period — a quartz oscillator — is connected to the first input of the logic element 35 of the input element 2, the second input of which is connected together with the first input of the logic element 3 to the output of the trigger 4. The output of the element And 2 is connected to the input of the counter 5 of the generator of 6 time intervals, the counter 5 consists of a serial connection To the counting ps of the decades 5-15-k, operating in a binary-controlled self-completing code, and the outputs of all bits decade count the tick 5 through the decoder 7 of the zero code is connected to the first input of the logic element OR B, the second input of which through the block 9 of the formation of the first

the measuring interval is connected to the output of the first counting decade 5-1 The second input of the logical element I 3 is connected through the shaper 10 pulses to the input bus 1I frequency meter and through the second shaper 12 pulses connected to the first input of the logical element I 13, the second

the input of which through the trigger 14 is connected to the bus 15 Starting and to the second input of block 9, and the output to the single input of the trigger 4 "Zero input

trigger 4, in turn, is connected to the zero input of the trigger 14 and the first input of the shift register 16, the counting input of which, together with the installation input to the multiplier 17

The code is connected to the output of the AND 3 logic element. The counting input of the multiplier 17 of the code is connected to the output of the AND 2 logic element, and the outputs of its binary bits are connected to the inputs of the binary digits of the decades of counter 5 through the gate group 18, the control input of which is connected to the input of register 16 shift connected to the output of the logical element OR 8 ,,

The binary bits of the shift register 16 are connected to the display device 19.

The unit 9 of forming the first measurement interval contains a logical element AND 20, the first input of which is connected to the output of the first decade 5-1, and the second input is connected to the k single output of the trigger 21, the single input of which is connected to the start bus 15, and the zero input is connected to output logic element

And 20 and the input of the logical element OR 8 about

The multiplier 17 code represents 40 45

normalized in amplitude and duration.

Claims (2)

The valve group 18 connects the binary bits outputs of the multiplier 55 17 code to the binary bits inputs of counter 5 so that the number contained in the code multiplier 17 when the control input of the valve is intelligent by a factor of 9 of that number of pulses period TD, which is received at its counting input. The result of the multiplication is obtained in real time. The pulse shaper 10 generates short, normalized in amplitude and duration impulses from the input measured signal. The pulse period of these pulses is equal to the period of the signal being studied with a frequency. The pulse shaper 12 forms pulses whose front coincides with the cut of the output pulses of the shaper 10. These pulses are also groups 18, the signal is recorded in counter 5 in an additional code. The digital frequency counter works as follows. In the initial state, the counter 5, the shift register 16 is set to zero, the trigger 4 and 14 are in the zero state, where there are no high potentials, their output elements, which are connected to the logic elements And 3 and 13, 2, and 13 are locked. The initial setup of these elements for simplicity is not shown in the drawing. The measured frequency signal arriving at the input bus 11 is converted in the pulse shaper 10 into short normalized pulses arriving at the closure of the logical element I 3 and the pulse shaper 12, which another pulse sequence is formed with the same period T 1 / f, but the fronts of the pulses of this sequence are formed at the moments of the pulse slices at the output of the shapes of the 0 тел body. and logic element 13. Measurement begins from the moment a trigger signal is applied to bus 15 to trigger the single inputs of flip-flops 14 and 21. Trigger 14 goes into one state under the action of this signal and triggers logic element AND 13 Trigger 21 under the influence of a pulse depending on its prior state, it either goes into a single state, or confirms this state, in which an enabling signal is sent to the logical element 20. The first after the opening of the element 13 and the pulse from the output of the driver 12 pulses passes through the logic element 13 and enters the single input of the trigger 4. The trigger 4 is transferred to the one state and allows the pulses from the source 1 of the sample periods to pass through the logical element 2 from counting inputs of counter 5 and code multiplier 17. Arrival at the input of counter 5 from the output of the logic element AND 2 pulses of exemplary periods Then the state of the first decade 15-1 begins to change. After ten 1A4 5-1 input goes imp pulses, the decade overflows, and at its output, connected to the counting decade 5-2 and with the logic element 20, a signal appears that passes through the logic element 20 and transfers the trigger 21 to the zero state and through the logic element RSh8 enters to the input of the shift register I6 and the control input of the valve group 18. Since during the time corresponding to the interval of ten periods T, the next pulse of the measured signal does not appear after the end of the output pulse of the former 10, a reverse counter from the output Yes, the logic element AND 3 pulses are not received and the shift signal, a shift by bit all information, practically does not change the code o, recorded in the shift register 16, By the same moment of the overflow of the decade 5-1, the same decade goes to the input of the code multiplier 17 signals, i.e. a code is formed in the multiplier, respectively. The corresponding number 90, the output impulse of the logical element OR 8, entering the control input of the valve group 18, opens the AND logical elements, with the result that the additional code of the number 90, i.e. code N - 90, where N is the capacity of the counter 5. Subsequent pulses from the output of the logical element 2 increase this code and the code existing in the multiplier 17 of the code. After 90 pulses go to counter 5 and multiplier 17 of the code (the total number of pulses T from the opening of the logical element I 2 is 100), counter 5 will overflow and return to the initial zero state, to which the decoder 7 will immediately respond the zero that generates a signal arriving at the logical element OR 8 and through it to the input of the shift register 16 and the control input of the gate group 18. If there were no pulses at the output of the IZ logical element in the interval of 100 Td, then the shift register will again register in all their razr ah, Isla 900 and the code at the outputs of the multiplier ode perepishets a counter 5 in the form of ode N - 900. Another T through 900 (i.e., after the total counting 1000 pulses with the period Tg) in the absence of signals at the output of the logical element; In the case of And 3, the decoder 7 of the zero code confirms zeroes in all bits of the shift register 16, the code of the number 9000 at the outputs of the multiplier 17 code rewrites into counter 5 as the code of the number N - 9000, etc. Thus, in the interval between the first pulse that passed the logical element I 13 and the first pulse at the output of the logical element I 3 (and this is practically the interval equal to T l / fy), the output of the logical element OR 8 receives a series of pulses, each i-th from which it is distant about the moment of opening the logical element I 2 by 10 T “The impulse, at the output of the logical element I 3, is fed to the reset input of the multiplier 17 of the code and to the counting input of the shift register 16. In the multiplier 17 of the code, this pulse transfers the total counter of the multiplied code to the zero state, after which the multiplayer begins the multiplication process from the beginning, since the counting pulses with the period TQ continue to flow to its counting input from the logic element AND 2. The pulse, which appeared on the counting input of the shift register 16, translates the first decade of the register to a state. Further, the device continues to work in the same way: the pulses of the sequence under investigation from the output of the logical element 3 and 3 turn the counter of the multiplier 17 code, causing it to start counting from by multiplying by 9 s zero, and increment the code fixed in the de / h l cade (first) register 16 shift, by one. This continues until the next pulse arrives from the output of the depotfrarator 7 of the zero code. At the moment of the occurrence of this pulse in the first decade of the shift register, the number N was recorded, corresponding to the first significant digit of the measured frequency, and the counter of the code 17 key recorded the number 9 dT / Td, where dT is the difference between the duration of the interval from the opening of the logical element 2 until the pulse at the output of 1 146 decoder 7 code zero and the duration of the interval in N T. The pulse from the output of the logical element OR 8 goes to the gate group 18, which fixes in the counter 5 code corresponding to N9, and to the input of shift register 16, which moves the code of the number Nj from the first decade to the second, the code O in all subsequent decades, and provides the code of the number O in the first decade. Further, the frequency meter operates in the same way: in the time interval between the signals at the output of the CMM 8 logical element, equal to (9 TuTd) T, 9 lT, the first decade of the shift register 16 counts the number N of pulses at the output of the IZ logical element; , each of these pulses nulls the multiplier counter of the 17th code, forcing it to start counting with multiplication by 9 seconds zero. The next impulse from the output of the decoder 7 of the zero code forms in the counter 5 a code of the number N - 9TТ / Т „, where & T „- the interval between the moment of occurrence of the signal at the output of the decoder code zero and the moment of occurrence of the preceding pulse at the output of logic element 3, and also shifts information in shift register 16: code K, from the second decade rewrites to the third, code N from the first decade rewrites to the second, forms the code of the number . About in the first decade and confirms the zeros in all senior bits, starting with the fourth. This principle of frequency counter operation is repeated until all decades of the shift register have been filled. ha In this case, the output signal of the element OR 8, non-shifting information in the shift register, arrives at the output of the shift register Ib, from where the zero inputs of the flip-flops 4 and 14 follow. Both flip-flops go to the zero state, And 2 and 13 are locked and the frequency counter stops measuring. The display of the display 19 displays the measurement result. For repeated measurement, a signal can be sent to the start-up bus 15. The technical advantages of the proposed device are to simplify the meter, increase its technical efficiency, reduce the cost with the same accuracy and characteristics as in the well-known .. Invention 5 Digital frequency meter according to the author. St. No. 1190285, characterized in that, in order to simplify it. The formating unit of the first measuring unit 275 148 is made in the vnde serially connected trigger and element, the second input of which is connected to the output of the first decade of the counter; Steralum, Start bus is connected to a single trigger input.