SU1555841A2 - Device for monitoring pulse series - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computer technology to control the transmission and processing of information. A device for monitoring a series of pulses contains an element OR 1, elements AND 2, 9, 10 and 20, memory register 3, input buses 4, drivers 5 - 7 pulses, pulse counter 8, gate generator 11, delay element 12, triggers 13 - 15, bus 16 "Continue monitoring", bus 17 "Failure", display bus 18, bus 19 clock pulses, code bus 21, bus 22 false pulse. Ensuring the possibility of determining the type of failure and providing the ability to control when the pulse sequence of the input sequences changes, allows the device to expand its functionality. 1 hp f-ly, 2 ill.

Description

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The invention relates to a pulse technique, can be used in automatics and computer technology to control the transmission and processing of information and is an improvement to the device according to the author. St. No. 1175022.

The purpose of the invention is to enhance the functionality by enabling the determination of the type of JQ failure and the ability to control when changing the pulse duration of the input sequences.

FIG. 1 shows the structural - electrical circuit of the device; j Figs 2 shows timing diagrams explaining the operation of the device.

The device contains an OR 1 element, whose inputs are bitwise connected to the inputs of the first element AND 2, also bitwise with the information inputs of the memory register 3 and also bitwise to the input buses 4. The output of the OR element 1 is connected to the inputs of the first 5 and second 6 drivers pulses. The output of the imaging unit 6 is connected to the input of the third imaging unit 7 pulses, the reset input of the counter 8 pulses, the first input of the second element And 9 and the second input of the third element And 10, the first input of which is connected to the output of the gates generator 11, the reset input of which is connected to the output of the imaging device 7 and the input element 12 delay. The output of the imaging unit 5 is connected to the R-input of the first trigger 13, the output of which is connected to the reset input of the register 3 and to the S-input of the second trigger 14. The output of the And 9 element is connected to the S-input of the third trigger 15, the first R-input of which is connected to the bus Continue monitoring 16, and the direct output - with the third input of the element And 10 and the output bus. Fault 17. The outputs of the register 3 form the bus 18 ing diction. The clock bus 19 is connected to the first input of the fourth element And 20, the information inputs of the counter 8 form a code bus 21, the output of the element 10 And is connected to the output bus False pulse 22. The output 50 of the driver 7 is connected to the S input of the trigger 13 and the write input of the counter 8 , the loan output of which is connected to the generator start input 11, and the subtraction input is connected to the output of element I 20, 55 whose second input is connected to the output of generator 11. The R input of the trigger 14 is connected to the output of element II 2, -a

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output - with the second input element And 9. The second R-input of the trigger 15 is connected to the output of the delay element 12, and the inverse output - to the clock input of the register 3.

The device works as follows t-time.

The controlled pulse series are formed by a set of pulses arriving at the input buses 4 of the device (Fig. 2, a, b and c).

These pulses can be shifted in time relative to each other and have a different duration. A series of pulses arrives at times t ,, ta, t}, t4 with a period T. If there are pulses on all input buses 4 and they coincide for a time sufficient for reliable operation of the device elements, on the leading edge of the first pulse from the element output OR 1 (Fig. 2, d) the pulse shaper 5 generates a pulse (Fig. 2, e), setting it to the state of logical 13 (Fig. 2, i).

The impulse from the output of the element AND 2 (Fig. 2, e) sets the trigger 14 to the state of the logical O (Fig. 2, k). Shaper 6 pulses at the falling edge of the pulse from the output of the element OR 1 generates a pulse (FIG. 2, g), which establishes a counter 8 in a logical state O and arrives at the inputs of elements 9 and 10 that do not pass it, since the triggers 14 and 15 are in a state of logical O and no alarms are generated.

Since the trigger 13 is in the zero state, the information received at the information inputs S-3, register 3 is written to the register. In the interval t t - t2, a failure signal is not generated and the trigger 15 remains in the initial state (Fig. 2, m). At the end of the first cycle of control, the pulse through the leading edge of the pulse from the output of the imaging unit 6, the imaging unit 7 (Fig. 2, a) generates a pulse that sets the trigger 13 into a single state (Fig. 2, i). This sets the state of logical 1 to trigger 14, and the information recorded in register 3 is erased (Fig. 3o). The pulse from the output of the imaging unit 7 to the counter 8 records the code of the selection interval of the CTS, arriving

from the code bus 21. The selection interval Tc is determined by the formula

TC T - AT / 2 Kt t

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where D.T. is the strobe duration determined by the instability of the period 8T and the instability of the duration of the input pulses;

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t0 is the clock period. Counter 8 starts counting the clock pulses from bus 19 to the subtraction input.

If at least one of the device device tires C does not have a pulse (the time moment tit in Fig. 2, a), then the output of the element 2 and the impulse does not form and the trigger 14 remains in one state, thereby allowing the passage of the impulse to the output of the element 9 (Fig. 2, l). In this case, the trigger 15 is switched to one state (Fig. 2, m) and a Failure signal is generated on the bus 17. After the time Tc after the formation of the first pulse from the output of the former 6, the counter 8 overflows. An impulse from the output of the counter 8 borrows a generator of 11 gates that generates a strobe pulse & T (Fig. 2, p). If the second pulse from the output of the imaging unit 6 hits the strobe, the output of element 10 does not pass, and along its falling edge, the imaging device 7 generates a pulse that resets the generator 11 of strobes and the counter 8. The duration of the strobulum does not reach the value & Since the inverse output of the trigger 15 is set to logic level O, the inputs of register 3 are blocked and information in the register is saved until a pulse from the output of delay element 12 (Fig. 2, n) is received at the second R input of trigger 15, after which the device is ready to control the next series of pulses. The delay time Ј of element 12 is chosen from the condition tu: Ј3: Tc, where ty is the pulse duration of the driver 7.

The presence of the signal level O on bus 22, the first discharge of bus 18 of the indication and the signal level logical 1 on bus 17 indicates that a pulse is passed on the first input bus.

If a spurious pulse (interval t t, Fig. 2, b) appears on one of the device inputs, then a pulse does not form at the output of the element And 2, the trigger 13 remains in one state and the pulse from the output is formed.

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The tel 6 enters through the element AND 9 to the S input of the trigger 15, switching it to one state (interval t} -i t, Fig. 2, l, m).

This impulse also arrives at the input of element I 10 and passes to the bus False impulse 22 (Fig. 2, p), since at this moment the logic level 1 is set at the output of the gate generator 11 (Fig. 2, p).

The presence of a logic 1 signal on the first discharge of the display bus 18 and on buses 17 and 22 indicates the arrival of a false pulse on the first input bus of the device.

Claims (2)

1. A device for controlling a pulse train according to the author. Ev, No. 1175022, which is due to the fact that, in order to expand the functionality by providing the possibility of determining the type of failure, a sequentially connected pulse counter, a strobe generator and the second element And, as well as the third element And, the element delays, output bus False pulse and clock bus, which is connected to the first input of the third element And, the second input of which is connected to the output of the strobe generator, and the output - to the subtraction input of the pulse counter, whose recording input is connected to the output a third pulse shaper and a reset input connected to the output of the second pulse shaper and the second input of the second AND gate, whose output is connected to 50 current momentum the output bus is a Lozh and the third input is with a direct output of the third trigger, which is designed as a trigger with two R-inputs, and the second R-input of the third trigger is connected via a delay element to the reset input of the strobe generator 55 pulses. 2. The device according to claim. Characterized in that, for the purpose of 71555841 the ability to control when changing the period of the pulses of the input sequences, the code bus is entered into it, and the counter eight pulses made in the form of a pulse counter with a preset, and the inputs of the preset pulse counter form a code bus.