SU527825A1 - Pulse counter - Google Patents

Description

one

The invention relates to computing.

A pulse counter on logical potential elements is known, containing in each bit two successively included memory cells interconnected by AND-NOT elements and buses of even and odd signals l. These counters are unreliable.

A pulse counter is known that contains memory cells, each of which consists of two elements interconnected by elements AND, the width of even and odd signals 2, However, the counter according to the proposed scheme, due to the spread of the characteristics of transistors, does not exclude memory that causes the counter to fail

2

The purpose of the invention is to simplify and increase the reliability of the circuit}, which is achieved by introducing into the counter the elements of OR-NOT and the reset bus of even and odd memory cells, with the inputs of the first element ORINE connected to the outputs of even-numbered cells

memory, and the output is connected to the first ;;. h. do the second element OR NOT: the second; i; -,: of which is connected with the length of even ciirjif r: and the output is connected to the W1 of the reset of the quotes: .r-- memory cells, inputs of the third element:; OR-NOT connected to the outputs odd) ;; -;., Memory cells, the output is connected to the first input of the fourth element OR-NOT% whose second input is connected to the S1 odd signals, and the output is connected to the mmie reset even memory cells.

The drawing shows the scheme of the device.

The pulse counter consists of a log1: an OR-NOT 1, CI element, 2 transistor memory cells 2, containing two OR-NOT 3, 4 logical elements (AND an odd number) interconnected by an AND 5 j element additionally entered of the OR-NOT logic elements and the trigger U of supplying pulses to and odd buses, the counting input of which is connected to the input 11 and 11, and the reset input is connected to the input of the OR-NOT 1 element and to the reset bar 12,

The counter works as follows.

Before starting work, bus 12 is given a reset pulse, as a result of which a single signal is received on an odd-numbered trigger bus 10, and on an even one, a zero signal. A reset pulse is also applied to the OR-NOT 1 element, at the output of which a single signal appears, causing memory cell 2 to be in one unit, and all other even memory cells to go to zero. The single signal of memory cell 2o is fed to the element OR-NOT 6, and the zero signal from element 6 to the element OR-NOT 7. The single signal from element 7 enters the odd-cell reset bus and drives all the odd cells to the zero state. A single signal of memory cell 2 simultaneously arrives at its element AND 5, thereby preparing the memory cell 2. to be triggered. When the first counting impulse appears on the input bus 11 on the even bus, a trigger 10 appears on a single signal, on an odd bus, a zero signal appears. The single signal from the even bus falls on the elements AND 5 of all even memory cells, but since only one element AND 5 cells of memory 2 is prepared for operation, only a single signal appears on it, the drive of this memory cell in single state and leaving the remaining cells in the initial position. The single signal of cell 2 prepares the AND 5 cell of memory 2 for triggering and is sent to the OR-NOT 8 element. At the same time, the output of the OR-NO 8 element is a zero signal, and since the odd-numbered bus is currently zero If there is no signal, then a delayed single signal appears at the output of the element OR-NOT 9, which is fed to the reset bus of even memory cells. Cell 2 returns from zero to zero. When the second counting pulse is applied, a zero signal appears on the even bus on trigger 10, and a single signal appears on the odd bus. The odd bus single signal triggers element AND 5 of memory cell 2. (a single signal appears at its output), putting cell 2 into one state, preparing its element AND 5 for actuation. Single cell signal 2 is applied to the element OR - NO 6, at its output a zero signal appears which is fed to the element OR NOT 7,

and since there is also a zero signal on the even bus at the moment, a single signal appears at the output of the OR-NOT 7 element. This single signal is fed to the reset bus in the initial state of the memory cells and drives the memory cell 2. to zero state.

When the next counting pulse is applied to the trigger 10, a single signal appears on the even bus, and a single signal appears on the even bus, and so on.

Claims (2)

In the proposed pulse counter scheme, the additional elements OR are NOT combined into two pairs, which are included in the reset buses of even and odd memory cells. This allows for a single-cell pulse counter to reduce the number of pairs of OR-NOT elements by n-1 / a times. In addition, the reliability of the uninterrupted operation of the meter is increased. The invention includes a pulse counter containing fl memory cells, each of which consists of two OR-NOT elements interconnected by AND elements, an even and odd-numbered bus, characterized in that, in order to simplify and increase reliability, additional OR-NOT elements and reset buses of even and odd memory cells, the inputs of the nej element OR-NOT are connected to the outputs of the even memory cells, and the output is connected to the first input of the second element OR-NOT, the second input of which is connected to the bus even signals, and o d is connected to the reset bus of odd memory cells, the inputs of the third element OR are NOT connected to the outputs of odd memory cells, the output is connected to the first input of the fourth element OR NOT, the second input of which is connected to the bus of odd signals, and the output is connected to the reset bus even cell n & mi. Sources of information taken into account in the examination of the invention: 1.Avt. St. USSR №291331, M. CL. H 03 K 5/159, 14.10.68. 2. Published in the Federal Republic of Germany No. 2345670, Cl. 21 a 1 3.6 / 22, H 03 K 23/02, published 04/07/74 (prototype).