SU563732A1 - Time switching device - Google Patents

Description

The device contains the first distributor 1, the outputs of which are connected to the inputs of the memory block 2 and to the control inputs of the keys Zl, ..., 3n, the signal inputs of which are supplied with information signals, and the outputs of the keys 32, ..., 3n are connected with the signal input of the shared key 4, the output of which is connected to the signal inputs of the additional keys 5i, 62, ..-, 5p. The control inputs of the keys 5 are connected to the outputs of the second distributor 6, the first input of which is connected to the output of the element 7 OR, the first input of which is connected to the first input of the first distributor 1, and the second input of the element 7 OR is given a start signal. In addition, the device contains an element 8 And, two odiovibrator 9 and 10, the subtractive counter 11 and the multi-input element 12 And, the inputs of which are connected to the zero outputs of the bits of the subtracting counter 11, and the first output with the control input of the common key 4 and the input of the first the one-shot 9, the output of which is connected to the first input of the first distributor 1. The outputs of the memory block 2 are connected to the single inputs of the bits of the detracting counter 11, the counting input of which is connected to the second input of the second distributor 6 and the output of the element 8 And, first whose input is connected to the second output of the multi-input AND element 12 and to the input of the second monostable multivibrator 10 whose output is connected to the third input of the second distributor 6. Yield OR element 7 is connected to a corresponding input of the subtracter counter II, and the second input element 8 and supplies the clock pulses.

The temporary switching device operates as follows.

After the trigger signal is applied to the second input of the element OR, the device is set to the zero state by the corresponding input of the subtracting counter 11 and the second distributor 6 and the logical unit is written to the first distributor 1. In the first distributor 1, the first output is excited, which opens the key 3i and generates signal at the first input of memory block 2. At the outputs of memory block 2, a first outgoing line address is formed, which according to the program must be connected to the first incoming line of the device. The generated address is written to subtraction counter 11.

From this moment on the second output of the multi-input element 12 I, a single potential appears, which is fed to the inputs of the element 8 AND and the second one-oscillator 10. At the output of the second one-oscillator 10 a pulse is generated, which is written to the second distributor 6 through its third input. Clock pulses received at the second input element 8 And, after passing through the open element 8 And, arrive at the counting input of the subtractive counter 11 and the second input of the second distributor 6. In the subtractive

the counter 11, with the arrival of each clock pulse, the recorded address of the outgoing line decreases by one. Accordingly, in the second distributor 6, a shift of the logical unit by one bit and a sequential excitation of its outputs occur. At the same time, signals that sequentially open these keys are generated at the control inputs of the additional keys 5i, 62, ..., 5n.

When a zero code is formed in the subtracting counter 11, a single potential is formed at the first output of the multi-input element 12, and at its second output -

zero potential. The single potential opens the common key 4, and the zero potential closes the element 8 And thereby stops the shift in the second distributor 6. The counting of pulses in

subtractive counter 11. At this moment, the potential from the output of the second distributor 6 opens only the specified additional key 5 and thus through the open keys 3i and 4 also forms the first connecting wire between the incoming line and the corresponding outgoing line.

The second connection path in the device for the incoming and corresponding outgoing line is formed in a similar way only after a signal from the output of the first one-Vibrator 9 with a delay shifts the unit in the first distributor 1 and through element 7 OR the zeroing subtracter counter and the second distributor 6. In the first distributor 1, only the second output is excited, the signal from which opens the key 32 and generates at the outputs of the memory 2 the address of that outgoing line, which according to the program must be

 connected to this incoming line.

Consequently, the shift of the unit in the first distributor 1 in succession, for the lanes, the whole switching program written in the memory block 2 is executed.

 each rod requires a number of clock cycles, which coincides with the number of the outgoing line that is switched in this rod.

In the proposed temporary switching device, the speed is 2 times higher.

compared to the famous.

Claims (1)

Invention Formula A temporary switching device contains its first distributor, the outputs of which are connected to the inputs of the memory block and control inputs of the p keys, the signal inputs of which are informational signals, and the outputs of the keys are connected to the signal input of the common key, the output of which is connected to the signal inputs of additional keys, the control inputs of which are connected to the outputs of the second distributor, to the first input of which connect the output of the OR element, the first input which is connected to the first input of the first distributor, and the second input of the OR element is given a start signal, characterized in that, in order to increase speed, an AND element, two single-oscillators, a subtractive counter and a multi-input AND element, whose inputs are connected to zero bit outputs are input subtractive counter, and the first output - with the control input of the shared key and the input of the first one-shot, the output of which is connected to the first input of the first distributor, while the outputs The memory stalk is connected to the single inputs of the bits of the detracting counter, the counting input of which is connected to the second input of the second distributor and the output of the element I, the first input of which is connected to the second output of the multi-input element Inc. to the input of the second one-oscillator, the output of which is connected to the third input of the second distributor, and the output of the OR element is connected to the corresponding input of the subtractive counter, and the second PULSE input element And clock pulses are given.