SU528612A1 - Asynchronous shift register - Google Patents

Description

the trigger is connected to the first control bus, and the second control bus is connected to the second input of the third additional trigger.

The drawing shows a functional diagram of the proposed synchronous shift register.

The register contains in each bit three triggers 1, 2, 3 on potential AND-NOT elements. The triggers have a counting input 4, installation inputs 5, 6, inverse and direct outputs 7, 8, output 9, installation inputs O 10, 11. The signals from output 9 indicate the end points of the transients in the corresponding trigger. The register also contains three additional flip-flops 12-14, performed on the OR-NOT elements and AND 15-19 elements, control bus 20, outputs of additional triggers 21-23, shift bus 24, AND-NOT elements 25-27.

At the inputs 5 and 6 of the trigger 1 bit, the signals “O and” 1 are constantly applied, respectively. Pins 10 and 11 are used as setup inputs only for triggers 2. All triggers in the register are connected in series, namely, outputs 7 and 8 of the previous trigger are connected to inputs 6 and 5 of the subsequent trigger, respectively.

An external control shift signal is supplied to bus 24, and an initial information setting signal is supplied to bus 20.

We will call the trigger set to zero if its “4” signal is sent to its common input 4. In this case, at its outputs 7 and 8, the signals “1 are set, at output 9 - the signal“ O. If the signal "1" is input to input 4, then the trigger stores information (the signal at one of the outputs is equal to "1, at the other -" O) and at output 9 the signal is equal to "1 When zeroing and recording information, a change in the value of the signal at output 9 indicates about the end of transients In the trigger.

Outputs 7 and 8 of all triggers are connected to the inputs of elements 15 additional triggers, and outputs 9 to the inputs of elements 18 additional triggers as follows: triggers 1, 2 and 3 of all bits - with additional triggers 12, 13 and 14, respectively. The direct outputs 22 and 23 of the additional triggers 13 and 14 are connected to the inputs 4 of the triggers 1 and 2, respectively.

An additional trigger works as follows. If the flip-flops connected to its inputs are set to zero, the signals on all inputs of element 15 are "O", on the inverse output of the trigger is set to "O, and on the input -" 1, since on all inputs of element 18 signals are equal to "O. This is true for the additional trigger 14 in the case when the signal "O is inputted to the input 20 of the element 19, if it is equal to" 1, then the signal "O" is set at the direct output. If all the triggers that are connected to the additional triggers store information, then on all inputs of the element 18 the signal is equal to "1. therefore

at the direct output of the additional trigger, in this case, the signal "O" is set, and at the inverse, "I," since at half the inputs of element 15, the signals will be equal to "O The value of the signal at the input of the element 19 in this case does not matter. Elements 16 and 17 serve to organize feedbacks. Thus, if the register triggers connected to the additional trigger are set to zero, then

at the output of the additional trigger signal

equal to "1 if they store information

or the input element 19, the signal "1, then

at the output of an additional trigger - “Oh.

In the initial state, the shift signal is

“Oh, the triggers 1 and 3 of each bit are reset to zero, the triggers 2 contain information. The stability of the initial state is provided as follows: at the output 23 of the additional trigger 14, the signal is equal to "1, on

the output 22 of the additional trigger 13 signal is equal to “O; at the output 21 of the secondary trigger 12, the signal is equal to“ O.

The cycle of operation of the register (shift by 1 bit towards the higher bits) consists of three

phases.

In the first phase, if the shift is enabled, the shift signal is changed from "O to" 1, allowing reception of information from flip-flops 2 to flip-flops 3. When recording ends, the output signal 23

the further trigger 14 becomes equal to "O", which will reset all triggers 2. At the output 22 of the secondary trigger 13, the signal "1. The phase is completed, triggers 3 store information, triggers 2 and 1 are cleared.

In the second phase, the signal “1 from the output 22 additional, trigger 13 allows the census from triggers 3 i-ro bits to triggers 1 (i + l) -ro bits. At the end of the recording process, the output 21 of the additional trigger 12 is set to “O. This signal is used to remove the shift resolution, after which the shift signal changes from "1 to" O. This causes all triggers 3 to be reset to zero. At output 23 of the last trigger 14, a signal "1." Phase is over. In triggers 1, the digit shifted by one bit in the direction of the higher bits is stored in the triggers. All triggers 2 and 3 are set to zero.

In the third phase, the signal "1 at the output 23 of the additional trigger 14 permits the census of information from the triggers 1 to the triggers 2.

Upon completion of the recording, the output signal 22 of the secondary trigger 13 will set the signal "O, which will reset the triggers 1, as a result of which the output 21 of the additional trigger 12 will set the signal" 1. All triggers 1 and 3

reset, triggers 2 store code shifted by one bit.

The shift cycle is over. The moment of the end of the shift by 1 bit is indicated by the change of the signal at the output 21 from "O to" 1. This signal is routed to the nerve control bus.

into the device controlling the shift, after which the next shift cycle can be started.

Setting the initial information is produced each time by inputs 10 and 11 of trigger 2 by the feed of mutually inverted values of the signals, the shift signal should be equal to "O". A signal "1" is applied to the input 20 (via the second control bus), and all the triggers 2 are nullified. The moment of the end of their zeroing is indicated at the output 22 by changing the signal from "O to". After that, the signal at input 20 should be changed from "1 to" O. The end of the installation process coincides with the moment of changing the signal at output 22 from "1 to" O.

The proposed shift register works according to the actual delays of the elements due to the indication of the end points of the transient processes. Tests have shown that this leads to an increase in register speed by 3-4 times compared with similar synchronous ones, increases reliability with respect to parametric faults of logic elements, and elements of the integrated indication diagnose possible device failures, which greatly simplifies the method of repair and troubleshooting.

In addition, an asynchronous shift register can be recommended for use in large integrated circuits, since internal clocking eliminates the need for synchronization clocks.

which significantly reduces the number of external findings.

Claims (3)

1. Auth. St. To 251617, cl. G PS 19/00, 1969 2. Auth. N ° 305589, cl. H OZK 23/00, 1971 3. Auth. St. 285054, cl. G PS 19/00, 1970 (prototype).